Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-12
2003-08-19
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S003000, C438S240000, C438S656000, C438S663000, C438S685000, C438S785000, C427S226000, C427S126300, C427S372200, C427S079000, C427S096400
Reexamination Certificate
active
06607980
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention in general relates to the fabrication of layered superlattice materials, and more particularly to a fabrication method that provides ferroelectric integrated circuit devices containing thin films of layered superlattice materials possessing high-polarizability, low fatigue and low-leakage current characteristics by using a low-temperature rapid-temperature pulsing anneal.
2. Statement of the Problem
Ferroelectric compounds possess favorable characteristics for use in nonvolatile integrated circuit memories. See Miller, U.S. Pat. No. 5,046,043. A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, and low leakage current. Layered superlattice material oxides have been studied for use in integrated circuits. U.S. Pat. No. 5,434,102, issued Jul. 18, 1995, to Watanabe et al., and U.S. Pat. No. 5,468,684, issued Nov. 21, 1995, to Yoshimori et al., describe processes for integrating these materials into practical integrated circuits. Layered superlattice materials exhibit characteristics in ferroelectric memories that are orders of magnitude superior to those of PZT and PLZT compounds.
A typical ferroelectric memory in an integrated circuit contains a semiconductor substrate and a metal-oxide semiconductor field-effect transistor (MOSFET) electrically connected to a ferroelectric device, usually a ferroelectric capacitor. Layered superlattice materials currently in use and development comprise metal oxides. In conventional fabrication methods, crystallization of the metal oxides to produce desired electronic properties requires heat treatments in oxygen-containing gas at elevated temperatures. The heating steps in the presence of oxygen are typically performed at a temperature in the range of 800° C. to 900° C. for 30 minutes to two hours. As a result of the presence of reactive oxygen at elevated temperatures, numerous defects, such as dangling bonds, are generated in the single crystal structure of the semiconductor silicon substrate, leading to deterioration in the electronic characteristics of the MOSFET. Good ferroelectric properties have been achieved in the prior art using process heating temperatures at about 700° C. to crystallize layered superlattice material. See U.S. Pat. No. 5,508,226, issued Apr. 16, 1996, to Ito et al. Nevertheless, the annealing and other heating times in the low-temperature methods disclosed in the prior art are in the range of three to six hours, which may be economically unfeasible. More importantly, the long exposure times of several hours in oxygen, even at the somewhat reduced temperature ranges, results in oxygen damage to the semiconductor substrate and other elements of the CMOS circuit.
After completion of the integrated circuit, the presence of oxides may still cause problems because oxygen atoms from a thin film of metal oxide layered superlattice material tend to diffuse through the various materials contained in the integrated circuit and combine with atoms in the substrate and in semiconductor layers, forming undesired oxides. The resulting oxides interfere with the function of the integrated circuit; for example, they may act as dielectrics in the semiconducting regions, thereby forming virtual capacitors. Diffusion of atoms from the underlying substrate and other circuit layers into the ferroelectric metal oxide is also a problem; for example, silicon from a silicon substrate and from polycrystalline silicon contact layers is known to diffuse into layered superlattice material and degrade its ferroelectric properties. For relatively low-density applications, the ferroelectric memory capacitor is placed on the side of the underlying CMOS circuit, and this may reduce somewhat the problem of undesirable diffusion of atoms between circuit elements. Nevertheless, as the market demand and the technological ability to manufacture high-density circuits increase, the distance between circuit elements decreases, and the problem of molecular and atomic diffusion between elements becomes more acute. To achieve high circuit density by reducing circuit area, the ferroelectric capacitor of a memory cell is placed virtually on top of the switch element, typically a field-effect transistor (hereinafter “FET”), and the switch and bottom electrode of the capacitor are electrically connected by a conductive plug. To inhibit undesired diffusion, a barrier layer is located under the ferroelectric oxide, between the capacitor's bottom electrode and the underlying layers. The barrier layer not only must inhibit the diffusion of oxygen and other chemical species that may cause problems—it must also be electrically conductive, to enable electrical connection between the capacitor and the switch. The maximum processing temperature allowable with current barrier technology is about 700° C. At temperatures above 700° C., the highest-temperature barrier materials degrade and lose their diffusion-barrier properties. On the other hand, the minimum feasible manufacturing process temperatures of layered superlattice materials used in the prior art is about 800° C., which is the temperature at which deposited layered superlattice materials, such as strontium bismuth tantalate, are annealed to achieve good crystallization.
It is common in the art to use rapid thermal processing (“RTP”) before furnace annealing to improve ferroelectric or dielectric properties of deposited metal oxide thin films, in particular, of layered superlattice materials. Methods using RTP before oxygen annealing are described in U.S. Pat. No. 5,648,114, issued Jul. 15, 1997 to Paz de Araujo et al. and U.S. Pat. No. 5,825,057, issued Oct. 20, 1998 to Watanabe et al. The RTP disclosed in the prior art is typically conducted at a temperature of 700° C. to 850° C. for a hold time of about 30 seconds, followed by an oxygen furnace anneal at 800° C. for 30 to 60 minutes. These process temperatures exceed the desired range described above, which does not exceed 700° C.
For the above reasons, therefore, it would be useful to have a low-temperature method for fabricating layered superlattice materials in ferroelectric integrated circuits that minimizes the time of exposure to oxygen at elevated temperature, as well as reduces the maximum temperatures used.
SOLUTION
The embodiments of the present invention reduce fabrication processing temperatures and reduce the time of exposure of the integrated circuit to oxygen gas at elevated temperature, while improving polarizability of the thin films of ferroelectric layered superlattice material.
An important feature of a method in accordance with the invention is a Rapid-Temperature Pulsing Anneal (“RPA”) technique. In an RPA, the temperature of a deposited thin film containing a plurality of metals is ramped up to a “hold temperature” at a rapid ramp rate, held at the hold temperature for a time period, the “holding time”, and then allowed to cool to a “cool temperature” before a “pulse sequence” of ramping, holding, and cooling is repeated one or more times. The rapid ramp rate, the hold temperature, the holding time, and cool temperature may vary between pulse sequences. Typically, a liquid precursor is deposited on a substrate, dried to form a solid film, and then an RPA is conducted. An RPA technique in accordance with the invention may also be used in combination with a CVD deposition process.
The RPA method may be conducted in an RPA apparatus similar or identical to a conventional rapid thermal processing (“RTP”) apparatus. A significant difference between an RPA technique in accordance with the invention and an RTP technique is that the heating, or rapid rise in temperature, of an RPA occurs a plurality of times in a pulse-like manner, in contrast to the unitary heating and holding time of a typical RTP. Another related significant difference is that the temperature of the treated material is typically, but not always, all
Paz de Araujo Carlos A.
Tanaka Keisuke
Uchiyama Kiyoshi
Patton & Boggs LLP
Smith Matthew
Symetrix Corporation
Yevsikov V.
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