Rapid equalizing ground line and sense circuit

Details Rapid equalizing ground line and sense circuit Rapid equalizing ground line and sense circuit

2001-11-27

2003-03-04

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S104000, C365S204000

Reexamination Certificate

active

06529431

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90124033, filed Sep. 28, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an equalizing ground line and sense circuit. More particularly, the present invention relates to a rapid equalizing ground line and sense circuit.
2. Description of Related Art
Most systems nowadays use read-only-memory (ROM) to serve as a single-chip memory for holding basic input/output programs. Hence, a fast data access speed for the ROM is important. To read a particular data bit from a cell o a ROM cell array, selection through ground line, bit line and word line is necessary. However, the selected ground line needs to provide a ground path for a cell current discharged to the ground, and the unselected ground lines need to be charged to a sensing level as other memory cells shielded. Hence, any design capable of shortening the charging/discharging period can immediately increase not only the operating speed of the ROM device but also the entire system.
FIG. 1
is a schematic circuit diagram of a conventional ROM unit. In the past, a circuit such as the one shown in
FIG. 1
was used to read off data stored in a selected memory cell. As shown in
FIG. 1
, the drain terminal of an NMOS transistor
114
inside the ground line circuit
100
couples with the output terminal of an inverter
108
. The drain terminal of an NMOS transistor
116
couples with the output terminal ok an inverter
110
. The drain terminal of an NMOS transistor
118
couples with the output terminal of an inverter
112
. A reference voltage REF
1
inputs to the gate terminal of the NMOS transistors
114
,
116
and
118
. Each ground line couples with the source terminal of the NMOS transistor. When a low potential is applied to the input terminal YGL
0
of the inverter
108
, the PMOS transistor inside the inverter
108
is conductive so that the ground line
124
is pre-charged to a preset voltage, which is related to the reference voltage REF
1
. On the other hand, when a high potential is applied to the input terminal YGL
0
of the inverter
108
, the NMOS transistor inside the inverter
108
is conductive and the reference voltage REF
1
turns on the NMOS transistor
114
so that the ground line
124
is coupled with the ground.
In
FIG. 1
, each ground line utilizes an inverter and an NMOS transistor to control pre-charging and discharging. However, this generates five related problems. In the discharging state, since the gate terminal of the NMOS transistor
114
couples with the reference voltage REF
1
, not a voltage source, the NMOS transistor
114
is turned into a resistor with high resistance leading to an extension of discharging period for the ground line
124
. In addition, since each ground line has an independent pre-charging path, an initial voltage may not be the same at a subsequent sensing operation such that some address may shift during the transient leading to data delay or reading failure. Moreover, when the ground line
124
is pre-charged to over 80%~90% of the preset potential, the pre-charge efficiency be comes worse due to the NMOS transistor
114
a working in a linear region potential. Therefore, a longer period is required in the charging process. Another problem is the coupling of the reference voltage with the ground line. Due to a transient change in the ground line, the reference voltage is de-stabilized. A final problem of the circuit is that each ground line needs to have an NMOS transistor. Hence either difficult layout design has to be implemented or else some odd layout may have to be chosen.
FIG. 2
is a schematic circuit diagram showing another conventional ROM unit. After reading data from the memory cell such as the NMOS transistor
218
inside the memory array
216
via the sense data circuit
204
, the NMOS transistor
210
and the NMOS transistor
214
, the sensing device
200
triggers the NMOS transistor
214
to return to the cut-off state. The circuit waits until another memory cell
218
is selected. The input terminal of the inverter
208
outputs a high potential so that the NMOS transistor
206
and the NMOS transistor
210
are both in a conductive state. Hence, a charging path from the voltage source VDD to the bit line connected to the NMOS transistor
214
is created. A data sensing operation is initiated until a parasitic capacitance of the bit line connected to the NMOS transistor
214
is charged up to a preset potential. Thus, to rad from a particular memory cell, the chip must wait the full charging period of the parasitic capacitor. Since any actual data sensing operation can be started only after the parasitic capacitor charging period, time is wasted.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a rapid equalizing ground line and sense circuit such that routing of ground lines is simplified. A second object of the invention is to shorten pre-charging time for the ground lines. A third object of the invention is to avoid direct coupling of ground line circuit and reference voltage to the ground lines so that a stable reference voltage is produced. A fourth object of the invention is to shorten discharging time of the ground line circuit and increase data sensing speed through a reduction of ground line resistance. A fifth object of the invention is to pre-charge the bit line before initiating a sensing operation via the sense circuit. Hence, data can be directly read from the memory cell without having to wait for the charging of the parasitic capacitor in the NMOS transistor.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a rapid equalizing ground line circuit. The ground line circuit includes a reference transistor, a switching circuit and a pre-charging bus. The switching circuit couples with the pre-charging bus and a ground voltage. The first terminal of the reference transistor receives a voltage source. A gate terminal of the reference transistor receives the reference voltage. The pre-charging bus couples with the second terminal of the reference transistor and the switching circuit.
Each switching circuit couples respectively with the ground voltage and corresponding ground line for receiving corresponding ground signal and inverted round signal and selecting corresponding ground line potential according to the ground signal and the inverted ground signal.
When a selected ground line signal changes from enable to disable and the selected inverted ground line signal changes from disable to enable, the corresponding ground line of the selected switching circuit changes from coupling with ground voltage into coupling with the pre-charging bus. Meanwhile, the corresponding ground line and all of the other non-selected ground lines couple with the pre-charging bus to initiate a pre-charging operation.
When the ground line signal is disabled and the inverted ground line signal is enabled, the corresponding ground line couples with the pre-charging bus to initiate a pre-charging operation. If the selected ground line signal is enabled and the selected inverted ground line signal is disabled, the selected switching circuit initiates a data sensing operation. Meanwhile, the corresponding ground line of the non-selected switching circuit couples with the pre-charging bus so that the pre-charging operation is continued.
The switching circuit further includes a first transistor and a second transistor. A first terminal of the first transistor couples with a ground voltage. A gate terminal of the first transistor receives a ground line signal. A first terminal of the second transistor couples with the pre-charge bus. The second terminal of the second transistor couples with a second terminal of the first transistor and a corresponding ground line of a memory cell. The gate terminal of the second transistor receives an inverted ground signal.
This invention als

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