Random access memory (RAM) capacitor in shallow trench...

Details Random access memory (RAM) capacitor in shallow trench... Random access memory (RAM) capacitor in shallow trench...

2007-08-28

2007-08-28

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S248000, C438S253000, C438S386000, C438S391000, C257SE21008

Reexamination Certificate

active

11223287

ABSTRACT:
A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI) The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask is used to etch bottle-shaped recesses in the STI under a first hard mask. After forming bottom electrodes in the recesses and forming an interelectrode dielectric layer, a conducting layer is deposited sufficiently thick to fill the recesses and to form a planar surface, and a second hard mask is deposited. The conducting layer is patterned to form the capacitor top electrodes. This reduced topography results in reduced leakage currents when the gate electrodes are formed over the capacitor top electrodes.

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“The Ideal SoC Memory: IT-SRAM” Leung et al., pp. 32-36, Proceedings of the IEEE 2000.

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