Random access memory device capable of minimizing sensing noise

Details Random access memory device capable of minimizing sensing noise Random access memory device capable of minimizing sensing noise

2000-07-08

2002-01-08

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000

Reexamination Certificate

active

06337823

ABSTRACT:

FIELD OF THE INVENTION
The present invention is in the field of semiconductor integrated circuit devices and is more specifically related to a dynamic random access memory device that minimizes noise induced by sense amplifier circuits.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a conventional dynamic random access memory device. In
FIG. 1
, each memory cell MC includes an access transistor
10
acting as a switch and a capacitor
12
holding a data bit. Gates of access transistors
10
in the same row i are connected to a common word line WLi (i=1, 2, 3, . . . , m) for the row. Sources of access transistors
10
in a column j are alternately connected to a corresponding pair of bit lines BLj and BLjB (j=1, 2, 3, . . . , n). One of the electrodes of each capacitor
12
is coupled to a drain of a corresponding access transistor
10
, and the other electrode thereof is coupled to a plate voltage Vp.
When a row address signal is applied, a row decoder
14
decodes the row address signal and activates a word line corresponding to the decoded row address signal to thereby turn on all access transistors
10
of memory cells MC coupled to the activated word line. Charges representing data, which are stored in all capacitors
12
of the memory cells corresponding to the activated word line, flow to corresponding bit lines via corresponding access transistors
10
. Sense amplifier circuits
16
sense and amplify very small voltage difference resulting from charge flowing to corresponding bit lines. Each of the sense amplifier circuits
16
responds to signals LAPG and LANG from a sense amplification activation signal generator
22
and drives a lower voltage on a bit line to a ground voltage VSS and a higher voltage of a bit line to an internal power supply voltage VCCA. An input/output gate circuit
20
transfers the amplified bit line signals to a data output buffer
24
.
FIG. 2
is a circuit diagram of the sense amplification activation signal generator
22
illustrated in FIG.
1
. This embodiment of the sense amplification activation signal generator
22
includes four inverters INV
1
, INV
2
, INV
3
, and INV
4
connected as illustrated in FIG.
2
. Herein, the inverters INV
2
and INV
3
serve as a buffer. The generator
22
provides a sense amplification activation signal LAPG at a high level and a sense amplification activation signal LANG at a low level when a row active command signal (e.g., a word line enable signal) is at a low level. On the other hand, the generator
22
provides the signal LAPG at a low level and the signal LANG at a high level when the row active command signal is at a high level.
FIG. 3
is a circuit diagram showing sense amplifier circuits
16
. Each of the sense amplifier circuits
16
is coupled between bit lines of a corresponding pair of bit lines, and is composed of two PMOS transistors MP
1
and MP
2
and two NMOS transistors MN
1
and MN
2
connected as illustrated in FIG.
3
. First current electrodes of the PMOS transistors MP
1
and MP
2
in each of the sense amplifiers
16
are commonly coupled to a signal line LA, and first current electrodes of the NMOS transistors MN
1
and MN
2
are coupled to a signal line LAB. The signal line LA is connected to an internal power supply voltage VCCA via a PMOS transistor MP
3
, which the sense amplification activation signal LAPG switches. The line LAB is connected to a ground voltage VSS via an NMOS transistor MN
3
, which the sense amplification activation signal LANG switches.
When a word line is selected, one of the respective bit lines of each pair changes to a voltage lower or higher than a precharge voltage (e.g., VCC/2), while the other bit line remains at the precharge voltage. In each sense amplifier circuit
16
, bit line voltages turn on one of the PMOS transistors MP
1
and MP
2
and one of the NMOS transistors MN
1
and MN
2
. When the sense amplification activation signals LAPG and LANG are activated respectively low and high, the signal lines LA and LAB are coupled to VCCA and VSS through corresponding transistors MP
3
and MN
3
, respectively. Thus each sense amplifier circuit
16
amplifies bit line voltages of a corresponding pair of bit lines BLj and BLjB to voltages VCCA and VSS or voltages VSS and VCCA.
Operating characteristics of a semiconductor integrated circuit or a MOS transistor change as the operating voltage varies. For example, if the operating voltage decreases, an operating speed of the MOS transistor decreases. On the other hand, if the operating voltage increases, the operating speed increases. This is because the carrier (electron or hole) mobility of the MOS transistor increases with operating voltage. For this reason, generator
22
asserts the signals LAPG (HVCC) and LANG (HVCC) faster when the operating voltage (internal power supply or external power supply voltage) is high and asserts signals LAPG (LVCC) and LANG (LVCC) more slowly when the operating voltage is low.
FIG. 4
illustrates the timing of signals in the high and low supply voltage cases.
According to the conventional sense amplification activation signal generator
22
, when a power supply voltage is high, noise such as power supply voltage bouncing or ground voltage bouncing is higher. Such noise may occur when multiple sense amplifier circuits
16
operate. As an internal power supply voltage (or an external power supply voltage) increases, rise/fall time of the respective signals LAPG and LANG (or the time required to turn on a transistor) becomes shorter. If the rise/fall time becomes shorter, the amount of current instantly supplied through each MOS transistor, i.e., the peak current increases. Because the signals LAPG and LANG simultaneously switch many transistors MP
3
and MN
3
, the peak current may further increase when the transistors MP
3
and MN
3
simultaneously turned on, resulting in greater noise such as the power supply voltage bouncing and the ground voltage bouncing. This increases noise (referred to as a sensing noise) when sense amplifier circuits
16
operate simultaneously.
The power supply voltage bouncing and the ground voltage bouncing can cause a malfunction in peripheral circuits. In particular, in a dynamic random access memory supporting a bank operation, such bouncing from operation of one bank affects operation of another bank. Accordingly, circuits and methods for minimizing the sensing noise resulting from operation of sense amplifier circuits are sought.
SUMMARY OF THE INVENTION
The embodiments of the present invention provide a random access memory device capable of minimizing sensing noise that causes variation of an operating voltage.
The advantages and features of the present invention can be exhibited in a dynamic random access memory (DRAM) device. The DRAM device includes: a memory cell array for storing data; a plurality of bit line pairs coupled to the memory cell array; and a plurality of sense amplifier circuits coupled to respective bit line pairs. In response to first and second sense amplification activation signals, each of the sense amplifier circuits senses a voltage difference between bit lines of a corresponding pair and amplifies the sensed voltages to a first and second power supply voltages or to the second and first power supply voltages. A sense amplification activation signal generating circuit generates first and second sense amplification activation signals in response to a row active command signal. The sense amplification activation signal generating circuit includes: a voltage comparator; a first signal generator, a second signal generator, and a switch. The voltage comparator compares a third power supply voltage with a reference voltage to generate a comparison signal. The first signal generator generates the first and second sense amplification activation signals of a first rise/fall time in response to the row active command signal. The second signal generator generates the first and second sense amplification activation signals of a second rise/fall time, which is delayed more than the first rise/f

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