Random access memory arrangements

Details Random access memory arrangements Random access memory arrangements

1981-09-14

1983-11-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1300

Patent

active

044159943

ABSTRACT:
A random access memory arrangement for reading data out of and into a random access memory asynchronously, for example, to effect time base correction of a digital television signal, comprises a random access memory having common read and write data terminals, an input circuit for supplying input data to said read and write data terminals for writing in the random access memory, a first output latch circuit connected to the read and write data terminals, a second output latch circuit connected to the first latch circuit, and means for supplying control signals to enable the random access memory to write the input data therein at given addresses in synchronism with write pulses of a write pulse signal, to enable the random access memory to read output data from given addresses therein in synchronism with read pulses of a read pulse signal, the read pulse signal being asynchronous with the write pulse signal, to control the first output latch circuit to hold and to supply to the second output latch circuit data supplied to the first latch circuit immediately prior to each write pulse, and to pass therethrough to the second latch circuit data supplied to the first latch circuit at all other times, and to control the second latch circuit to hold the data supplied to it by the first latch circuit immediately prior to the beginning of each read pulse until the beginning of the next succeeding read pulse and to supply the data so held to an output of the arrangement.

REFERENCES:
patent: 3402398 (1968-09-01), Koerner et al.
patent: 3560940 (1971-02-01), Gaensslew

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