Static information storage and retrieval – Read/write circuit – Precharge
Patent
1994-02-25
1994-11-15
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Precharge
365177, 36518901, 365205, 327 55, G11C 700
Patent
active
053654838
ABSTRACT:
A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may De internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.
REFERENCES:
patent: 4354257 (1982-10-01), Varshney et al.
patent: 4601017 (1986-07-01), Mochizuki et al.
patent: 4612631 (1986-09-01), Ochii
patent: 4616148 (1986-10-01), Ochii et al.
patent: 4636985 (1987-01-01), Aoki et al.
patent: 4733112 (1988-03-01), Yamaguchi
patent: 4740926 (1988-04-01), Takemae et al.
patent: 4764901 (1988-08-01), Sakurai
patent: 4816706 (1989-03-01), Dhong et al.
patent: 4825110 (1989-04-01), Yamaguchi et al.
patent: 4831287 (1989-05-01), Golab
patent: 4843264 (1989-06-01), Galbraith
patent: 4845381 (1989-07-01), Cuevas
patent: 4845672 (1989-07-01), Watanabe et al.
patent: 4845675 (1989-07-01), Krenik et al.
patent: 4866674 (1989-09-01), Tran
patent: 4871978 (1989-10-01), Galbraith
patent: 4893278 (1990-01-01), Ito
patent: 4899317 (1990-02-01), Hoekstra et al.
patent: 4901284 (1990-02-01), Ochii et al.
patent: 4903238 (1990-02-01), Miyatake et al.
patent: 4914634 (1990-04-01), Akrout et al.
patent: 4947376 (1990-08-01), Arimoto et al.
patent: 4975877 (1990-12-01), Bell
patent: 4984204 (1991-01-01), Sato et al.
patent: 5019725 (1991-05-01), Yoshino
patent: 5030853 (1991-07-01), Vinal
patent: 5111078 (1992-05-01), Miyamoto et al.
patent: 5192878 (1993-03-01), Miyamoto et al.
patent: 5304874 (1994-04-01), Vinal
patent: 5305269 (1994-04-01), Vinal
International Search Report, PCT/US92/04630, dated 30 Sep., 1992.
High-Sensitivity, High-Speed FET Sense Latch, Bishop et al., IBM Technical Disclosure Bulletin, vol. 18, No. 4, Sep. 1975, pp. 1021-1022.
Current-Mode Techniques for High-Speed VLSI Circuits With Application to Current Sense Amplifier for CMOS SRAM's, Seevinck et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 525-535.
High Density SRAMs, Ochii et al., IEEE International Solid-State Circuits Conference, 1985, pp. 64-65.
8ns CMOS 64kx4 and 256kx1 SRAMS, Flannagan et al., IEEE International Solid-State Circuits Conference, Feb. 15, 1990, pp. 134-135, 282, 100-101.
MOS Digital Circuits, Sedra et al., Microelectronic Circuits, Holt, Rinehart and Winston, Inc. 1987, pp. 846-849, 231-234.
LaRoche Eugene R.
Thunderbird Technologies, Inc.
Yoo Do Hyun
LandOfFree
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