Random access memory apparatus

Details Random access memory apparatus Random access memory apparatus

1987-02-10

1988-12-27

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365233, G11C 700

Patent

active

047945664

ABSTRACT:
A random access memory apparatus suitable for sequential write
on-sequential read, for example in a digital video special effects unit, comprises a write enable demultiplexer and a write address generator for demultiplexing incoming data into N channels A to D, where N is at least two, N memories in each of the N channels A to D, the incoming data allocated to any given one of the channels A to D being written into all of the memories in the given channel A to D, a read address generator for reading stored data from any one of the memories and, on reading from a memory, setting a busy flag for that memory, the busy flag being cleared N data periods later, and a busy flag control to control the read address generator to step onto a different memory in the same channel A to D as a memory to be read, when the memory to be read has a set busy flag. Apparatus is also provided for non-sequential write/sequential read and non-sequential write
on-sequential read.

REFERENCES:
patent: 4476548 (1984-10-01), Matsumoto et al.

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