Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-08-31
2001-01-30
DeCady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06182254
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Rambus application specific integrated circuit (ASIC), and more particularly, to a Rambus ASIC having a high speed testing function and a testing method thereof, in which a high speed test of 500MHz or greater is realized using a low frequency testing system.
2. Discussion of the Related Art
A conventional Rambus ASIC cell (RAC) will be described with reference to the accompanying drawings.
FIG. 1
is a schematic view illustrating a basic system of a Rambus memory.
FIG. 2
is a schematic view illustrating a conventional Rambus ASIC chip and a testing circuit thereof.
As shown in
FIG. 1
, the basic system of a Rambus memory includes a master device, a Rambus channel, and a slave device.
In other words, the master device adopts an ASIC chip
1
constituting an ASIC core
3
and a Rambus interface
4
, while the slave device adopts a Rambus DRAM (RDRAM) chip
2
constituting a Rambus interface
5
and a DRAM core
6
. Data input/output between the Rambus interface
4
of the ASIC chip
1
and the Rambus interface
5
of the RDRAM chip
2
is performed at high speed, while data input/output in the ASIC core
3
is performed at low speed.
The master device has an RDRAM as a general ASIC chip and a Rambus ASIC cell (RAC) as a Rambus interface for high speed data input/output.
The RAC in the master device can perform transaction request for the RDRAM chip.
An ASIC device, a memory controller, a graphic engine, a microprocessor, and the like are examples of the master device.
The slave device always respond to request from the RAC of the master device.
The operation test of the Rambus memory system will be described below.
As shown in
FIG. 2
, for the operation test of the Rambus memory system, there is provided a high speed test equipment system
20
in a Rambus ASIC chip
10
. The high speed test equipment system
20
drives or compares data at a speed of 500MHz or greater through each input/output (I/O) pin.
A data driver of the high speed test equipment system
20
applies a test pattern for operating an ASIC core
11
of the Rambus ASIC chip
10
to the ASIC core
11
through ASIC core input pins, and outputs data at a speed of 500MHz or greater through the RAC
12
from the ASIC core
11
.
The data of 500MHz or greater is input to a comparative channel of the high speed test equipment system
20
. The input data is compared with expected pattern data stored in a memory of the high speed test equipment system
20
and then tested.
High speed input/output test is performed to identify whether or not the Rambus ASIC chip
10
can output the data of 500MHz or greater through the RAC
12
.
The conventional Rambus ASIC chip testing method has a problem that, to correspond to the high speed operation of the RAC of the Rambus ASIC chip, the high speed testing system is required, which increases the test cost in mass production of the Rambus ASIC chip, thereby reducing cost competition.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a Rambus ASIC having a high speed testing function and a testing method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a Rambus ASIC having a high speed testing function and a testing method thereof, in which a high speed test of 500MHz or greater is realized using a low frequency testing system.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a Rambus ASIC having a high speed testing function according to the present invention includes a Rambus ASIC chip constituting a master device, which includes an RAC with a first data input/output speed, a Rambus DRAM constituting a slave device, a test comparator for driving or comparing data at a second speed lower than the first data input/output speed through each I/O pin in the Rambus ASIC chip, an operating clock supply part for supplying an operating clock to the RAC of the Rambus ASIC chip by varying the operating clock in data writing and reading under the control of the frequency of the test comparator, and a test logic part for outputting data input/output test signals to the test comparator by temporarily storing and comparing data writing/reading signals in the Rambus DRAM.
In another aspect, a testing method of Rambus ASIC having a high speed testing function includes the steps of setting an operating clock to correspond to the maximum operation speed of an RAC under the control of a test comparator, writing certain data in a slave device and compressing the data to store in a test logic part, reading out the data written in the slave device and compressing the data to store in the test logic part, comparing the written data stored in the test logic part with the read out data stored in the test logic part, determining normal data input/output through the RAC if the two data values stored in the test logic part are the same as each other, and repeating said testing steps by lowering the clock frequency of a clock supply part at a certain level.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5606717 (1997-02-01), Farmwald et al.
patent: 5638334 (1997-06-01), Farmwald et al.
Rambus Inc., Direct RAC Data Sheet, Rambus, p. 1 to 46, Aug. 1998.
Gasbarro, The Rambus Memory System, IEEE, p. 94 to 96, May 1995.
Gasbarro, Testing High Speed DRAMS, IEEE, p. 361, Feb. 1994.
Chase Shelly A
De'cady Albert
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
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