RAM with synchronous write port using dynamic latches

Details RAM with synchronous write port using dynamic latches RAM with synchronous write port using dynamic latches

1997-02-28

1999-08-03

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518902, 365193, 365194, 365210, 36523002, 36523008, 365233, G11C 700

Patent

active

059333693

ABSTRACT:
Dynamic latches for writing to a synchronous RAM are controlled by a clock signal and a delay circuit so that the dynamic latches will not stay in a latched state for more than a selected time interval regardless of the clock signal. One delay circuit limits the length of a write enable signal. Another delay circuit responds to the write enable signal and after a delay returns the address and data latches to their transparent states.

REFERENCES:
patent: 5566123 (1996-10-01), Freidin et al.
patent: 5687134 (1997-11-01), Sugawara et al.
patent: 5708614 (1998-01-01), Koshikawa

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