Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1995-04-17
1996-02-20
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365194, 36523006, 36523008, 327261, 327264, G11C 700
Patent
active
054935300
ABSTRACT:
A synchronous SRAM (or DRAM or other logic) chip with input registers (or latches) associated with the chip memory cell array input lines, where there is logic associated with the registers, locates the logic gates upstream of the registers and connected to the D input of each register. Hence the logic gates not only provide the needed logic function, but also provide the necessary delay to meet the specified hold time delay in synchronous circuits. This reduces the logic function after the input registers and hence improves the clock-to-output access time of the chip.
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Kao Y. S.
Lee Tsu-Wei F.
Tran Thinh D.
Zeman Richard J.
Klivans Norman R.
Mai Son
Nelms David C.
Paradigm Technology, Inc.
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