RAM with dual precharge circuit and write recovery circuitry

Details RAM with dual precharge circuit and write recovery circuitry RAM with dual precharge circuit and write recovery circuitry

1987-12-03

1989-01-31

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

365233, 365190, 365194, G11C 700, G11C 800

Patent

active

048021296

ABSTRACT:
A memory is written via data lines which are driven by a write driver. The data lines are coupled to a selected bit line pair as determined by a column address. The data lines are driven to a logic state representative of a data input signal by a write driver. The write driver is enabled during the presence of a write enable pulse. The write enable pulse is generated in response to a read mode to write mode transition and also in response to a transition of the data input signal. The data lines are precharged in response to a transition of the data input signal that occurs during the write mode.

REFERENCES:
patent: 4712197 (1987-12-01), Sood
patent: 4722074 (1988-01-01), Fujishiwa et al.

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