Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-04-13
2001-11-27
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S203000, C365S233500
Reexamination Certificate
active
06324122
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to electronic memories and more specifically to synchronous random access memory design.
2. Description of Related Art
Random access memory (RAM) is the most common type of memory found in computers, printers and other devices that use microprocessors. Memory is required in microprocessors because only data that is stored in memory can be manipulated. The two basic types of RAM are dynamic RAM (DRAM) and static RAM (SRAM). SRAM is faster and more reliable than the more common and less expensive DRAM.
SRAM is typically used for cache memory which is accessed frequently, and DRAM is used for main memory. Additionally, many systems allow for direct memory access (DMA) to RAM. DMA is a technique for transferring data from memory to a processor without passing it through a memory management system.
Regardless of whether and how a SRAM or DRAM is used and implemented, the overall architecture is somewhat standard. All RAM modules contain an array of memory cells and have peripheral circuits. A memory cell stores either a single bit of information (1 or 0) or a group of bits, depending upon the architecture of the RAM module. Each memory cell is defined by a unique address and accessed with peripheral circuits.
Synchronous RAM uses a clock signal to time the phases of operation of the RAM module. For active-high logic circuits, the set-up phase is performed during the high portion of the clock signal and the access phase (“AC phase”) during the low portion. The phases of an active-low circuit are performed in the opposite clock states.
Certain types of asynchronous RAM also use the set-up phase and the AC phase to time its operation. When a request is sent to the RAM, signal detection circuitry is used to initiate the set-up phase. A clock generation circuit, such as a boot-strap clock buffer, is then used to separate the AC phase from the set-up phase.
During the set-up phase, the address is decoded, the decision of whether to read or write is made, and, when necessary, the memory array pre-charges. The actual reading or writing to the memory cell is performed during the AC phase. Since both phases are necessary, only one complete read or write operation can be performed during a full clock cycle for a standard RAM module.
A DMA request, however, could occur at either the first half or the second half of a clock cycle. If a DMA request were received in the second half of a clock cycle, a RAM module would not be able to process the request until the next clock cycle, delaying the time that it would take to respond to the request. Additionally, the processor would need to arbitrate the DMA request. The microprocessor could only grant a DMA request by pausing its own use of the memory while allowing the device requesting the DMA to access the memory. Although dual port memory modules would allow for dual memory access during a single clock cycle, they are far too large and costly to be used regularly.
The cost effectiveness of RAM depends not only on the module's size, but also on the speed of the clock signal. A system with a clock signal that remains in its high state for longer than is needed to complete the set-up phase is inefficient. Similarly, it is inefficient for an RAM module to remain in its AC phase for longer than is required while the clock signal is low. Since the speed of a system clock is usually selected based on the requirements of the processor rather than to optimize operation of a RAM module, many RAM modules are unnecessarily idle.
What is needed is a synchronous RAM module that overcomes shortfalls of the RAMs currently known in the art.
BRIEF SUMMARY OF THE INVENTION
The present invention provides an improved RAM module synchronized with an external signal and a method for constructing the same. The RAM module includes a memory array, control circuitry, an address decoder, pre-charge circuitry, read circuitry and write circuitry. The memory array consists of a plurality of memory cells and their associated bit lines and word lines. The control circuitry is operably connected with and regulates the operation of the memory cells. The “control time” is equal to the interval required for the control circuitry to complete its most time-consuming operation. The address decoder can select any memory cell in the memory array within an “address time.” The pre-charge circuitry charges the bit lines of the memory array to a high state within a “set-up time.” The “critical set-up time” is equal to the longest of the control time, the address time or the pre-charge time. The read circuitry receives signals from the bit lines of the memory cells. The write circuitry replaces the signals stored by the memory cells. The most time consuming operation can be completed in a “read time” for the read circuitry and a “write time” for the write circuitry. The “critical AC time” is the time interval equal to the greater of the read time or the write time. A signal optimizer is operably connected to the control circuits and is capable of receiving the external periodic signal and transforming that signal into a higher frequency signal that maintains its high state for at least the critical set-up time and its low state for at least the critical AC time.
The method for designing the improved RAM module synchronized with an external signal according to the present invention begins with designing a preliminary architecture of an RAM module including a plurality of memory cells and peripheral circuits. A critical set-up time, a critical AC time, and an optimization factor must be determined. The critical set-up time is determined from the worst-case scenario circuit in the set-up phase, namely the operation that requires the most time to execute during the set-up phase. The critical AC time is determined from the worst-case scenario circuit in the AC phase. The optimization factor is a number representing how many times the critical set-up time added to the critical AC time will divide into the period of an external clock cycle. An optimization circuit must be designed that can receive a system clock signal as an input and output an optimized clock signal that has a frequency equal to the optimization factor times the frequency of the system clock signal. Additionally, the optimized clock signal must remain in its active state for at least the critical set-up time and in its inactive state for at least the critical AC time.
REFERENCES:
patent: 5767715 (1998-06-01), Marquis et al.
patent: 6166993 (2000-12-01), Yamauchi
patent: 6208183 (2001-03-01), Li et al.
Lee Eric W.
Nguyen Huy
Sun Bruce C.
Carr & Ferrell LLP
Dinh Son T.
Malino Morgan E.
Rosun Technologies
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