Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1996-11-04
2001-03-27
Yoo, Do (Department: 2187)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S052000
Reexamination Certificate
active
06209047
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to devices for transmitting data stored in a RAM (random access memory), and more particularly to devices for transmitting data stored in a RAM after temporally writing the data to a FIFO (first input first output) memory, and method a thereof.
The present application for a RAM data transmitting apparatus using FIFO memory, is based on Korean Application Serial No. 39610/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
In general, a device such as a compact disk read only memory (CD-ROM) decoder is provided with an externally connecting RAM. For the RAM connected to the CD-ROM decoder, commonly referred to as a dynamic RAM, data applied from outside (data read from a compact disk) is processed by being temporally written and read as required when signed processing operations are to be performed on the data. That is, the CD-ROM decoder performs required actions such as error correction by reading data from outside which is written on a RAM and then writes the corrected data again on the RAM. The data written on the RAM after error correcting is accessed and processed by a host computer.
In accessing data written on a RAM (hereinafter called RAM data) by a host computer, an intervening first-in first-out memory (hereinafter, called FIFO) is generally used between the RAM and the host computer. In other words, when the access to the RAM data is required by the host computer, the RAM data to be transmitted is written on and then read out from the FIFO memory. Conventionally, this transmitting action is controlled by an empty flag and a full flag indicating the state of the FIFO. A controller for controlling the operation of the FIFO determines the state of the FIFO using these empty and full flags and applies request for RAM data transmitting to a RAM controller which controls the operation of the RAM. Then, according to the RAM data transmitting request signal received from the FIFO controller, the RAM controller writes the RAM data on the FIFO. The host computer reads the RAM data written on the FIFO until it receives an indication the FIFO is empty from the empty flag.
When a RAM data transmitting request signal is generated in response to the empty flag as mentioned above, the RAM controller causes RAM data to be written on the FIFO. When the RAM data is written on the entire contents of the FIFO, the full flag is generated and the RAM data transmitting request signal is stopped. At this time, the generation of the full flag is canceled when the host computer reads the data written on the FIFO, and the RAM data transmitting request signal is then generated again. When the host computer accesses the RAM data written on the FIFO at every time when the FIFO is full, the result is that the RAM data transmitting request signal occurs frequently, at a timing in proportion to the access times. However, since the RAM is being used in many ways, the frequent RAM data transmitting request signals inefficiently provide for few for the RAM chances to be used in the other ways. When the transmission of the RAM data is required when the FIFO becomes empty, the data access action of the host computer is blocked so long as the FIFO remains empty. Therefore, it is difficult to continuously access the data.
SUMMARY OF THE INVENTION
It is therefore, an object of the present invention to provide a RAM data transmitting apparatus and a method thereof by which a RAM can be used for other functions during transmission of RAM data.
It is another object of the present invention to provide a RAM data transmitting apparatus and a method thereof by which a host computer can continuously access the RAM data.
It is yet another object of the present invention to provide a RAM data transmitting apparatus and a method thereof by which system performance can be improved by reducing the occurrence of RAM data transmission request.
It is an additional object of the present invention to provide a RAM data transmitting apparatus which generates a RAM data transmission request when RAM data of an arbitrarily selectable predetermined amount is contained in a FIFO, as well as a method of operating the novel apparatus.
To achieve the above objects of the present invention, there is provided a first-in first-out memory (FIFO), having a storage area, which generates a first flag when RAM data is written in the FIFO so as to fill a first area smaller than the total FIFO storage area while the RAM data is written in the FIFO from the RAM in response to the generation of a write enable signal. The FIFO memory generates a second flag when the RAM data is written in the FIFO so as to fill in a second area smaller than the total FIFO storage area and larger than the first area, and also generates a third flag when there is no remaining RAM data contained in the FIFO. A RAM data transmitting apparatus writes the RAM data from the RAM into the FIFO when the first flag is generated till the second flag is generated, and continuously accesses the RAM data stored in the FIFO to a predetermined data access until the third flag is generated when the second flag is generated. As a result, the RAM can be used for another purpose.
To achieve the above objects of the present invention, there is provided a RAM (random access) data transmitting apparatus having a RAM; a first-in first-out memory (FIFO) having a storage area, for sequentially writing a RAM data stored in the RAM in response to the generation of a write enable signal, and generates a first flag if the RAM data is written to fill a first area smaller than the total storage area; generates a second flag if the RAM data is written to fill a second area smaller than the storage area and larger than the first area; and generates a third flag if no RAM data is written in the FIFO memory; a controller for, if the first flag is generated, generating the write enable signal till the second flag is generated, whereby the RAM data stored in the RAM is written in the first-in first-out memory; and a data access circuit for, if the second flag is generated, continuously accessing the RAM data written in the first-in first-out memory until the third flag is generated.
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patent: 4864543 (1989-09-01), Ward et al.
patent: 4888739 (1989-12-01), Frederick et al.
patent: 4891788 (1990-01-01), Kreifels
patent: 5406554 (1995-04-01), Parry
patent: 5502655 (1996-03-01), McClure
patent: 5506809 (1996-04-01), Csoppenszky et al.
patent: 5640515 (1997-06-01), Park
patent: 5682554 (1997-10-01), Harrell
Portka Gary J.
Samsung Electronics Co,. Ltd.
Sughrue Mion Zinn Macpeak & Seas, PLLC
Yoo Do
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