Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-03
2002-03-05
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S596000, C438S633000, C438S683000
Reexamination Certificate
active
06352899
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor technology and more particularly to the method of forming silicide electrodes in active semiconductor devices, such as MOS transistors.
An important subject of ongoing research in the semiconductor industry is the reduction in the dimensions of devices used in integrated circuits. Planar transistors such as metal oxide semiconductor (MOS) transistors are particularly suited to use in high density integrated circuits. As the size of MOS transistors and other active devices decreases, the dimensions of the source, drain, and gate electrodes and the channel region of each device decreases correspondingly.
The design of ever smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junction regions. Shallow junctions are necessary to avoid lateral diffusion of implantation dopants into the channel during annealing and other process steps. Lateral diffusion is undesirable because it contributes to higher leakage currents and poor breakdown performance. Shallow source/drain regions, for example less than 1000 Å, and preferably less than 500 Å, are necessary for acceptable performance in short-channel devices.
When shallow-junction electrodes are used in transistors it becomes more difficult to provide reliable, low-resistance connections to the source/drain regions of the device. Metal-silicide contacts are a typical means of effecting such connections to source/drain electrodes. In the prior art, conductive metal is deposited on the silicon electrodes and annealed to form a metal-silicon compound on the surface of the electrodes. The compound, called silicide, is electrically and physically bonded to the electrode and has a substantially lower sheet resistance than the doped silicon on which it is formed. An important advantage of silicide contacts formed in this manner on small devices is that silicide is only formed where the deposited metal is in contact with silicon. By means of a selective etch, the metal is readily removed from the non-silicided area. Thus, the silicide regions are automatically aligned over only the electrode surfaces where underlying silicon is exposed on the source/drain regions. This self-aligned silicide process is generally referred to as the “salicide” process.
Unfortunately, the salicide process consumes a portion of the surface silicon that forms the underlying source/drain. This is because the metal-silicide is formed by a chemical reaction that occurs during an annealing step, when the deposited metal reacts with the underlying silicon. Electrodes with very thin junction depths have less silicon to sacrifice to the formation of silicide and can only permit a very thin layer of silicide to be formed. But thin silicide films are known to be thermally unstable and have an undesirably high sheet resistance. In the case of extremely thin junction depths, less than 500 Å, the sacrifice of silicon from the underlying junction will also significantly degrade junction performance.
It would be advantageous if an improved silicide process for ultra-thin junctions were available.
It would also be advantageous if the silicide layer provided a larger area to allow for subsequent contacts to be formed over the source/drain region.
SUMMARY OF THE INVENTION
Accordingly, a method is provided for forming MOS transistor structures on a silicon substrate. The method comprises defining a plurality of active areas on the substrate by forming one or more isolation regions to electrically isolate adjacent active areas from one another. Source and drain regions are formed in each active area. Electrode structures having electrodes and sidewalls are also formed on the substrate. The electrode structures can be either gate electrode structures, in which the electrode overlies a gate insulating layer, or interconnecting electrodes for connecting to active areas.
After forming the above structures, a contact material is deposited over the substrate and electrode structures. The contact material is preferably a deposited silicide. However, the contact material could initially be polycrystalline silicon.
The contact material is planed until level to remove excess contact material. The contact material is then electrically isolated from the electrodes. The electrical isolation can be accomplished by a selective etch back process, or continued planing to a predetermined level.
One preferred method comprises defining active areas on the substrate by forming one or more active area isolation regions to isolate adjacent active areas from each other. Source and drain regions are formed in each active area. Electrode structures are formed on the substrate, including a gate electrode structure in each active area, and interconnect electrode structures. The electrode structures preferably include electrode caps. Silicide is deposited over the entire wafer until it reaches a thickness at least equal to the height of the highest structure. The silicide is then planed until level. The silicide is then selectively etched with an etchant that etches the silicide faster than the electrode caps. The selective etch continues until the silicide reaches a level no higher than the top of the lowest electrode.
The method is suitable for forming silicided electrodes on a semiconductor substrate where devices such as MOS transistors are formed. The MOS transistor structure comprises a plurality of active areas formed on the substrate and isolated from adjacent active areas by isolation regions. A source region and a drain region are typically within an active area on opposite sides of a gate electrode. A source silicide region covers the source region and extends at least partially over the adjacent isolation regions. Likewise, a drain silicide region covers the drain region and extends partially over the adjacent isolation regions. By extending over the isolation regions, the silicide regions provide larger areas for subsequent electrical contact. The ability to provide larger areas by extending the silicide regions over the adjacent isolation regions also allows the source/drain regions to be made even smaller while maintaining sufficient area for electrical contact. Smaller source/drain regions in turn have lower capacitance and lower leakage currents.
The silicide material deposited to form the MOS transistor structures is preferably a combination of silicon and one or more metals selected from the group consisting of refractory and noble metals. Suitable examples of silicide materials used with the present invention include, but are not limited to, TiSi
2
, TaSi
2
, WSi
2
, CoSi
2
, NiSi or a combination thereof The silicide material is preferably deposited to a thickness of between approximately 2000 Å and 5000 Å over the entire area of the substrate using a chemical vapor deposition (CVD) process.
The step of planing the silicide is preferably carried out using a chemical mechanical polish (CMP) process. The CMP process preferably stops at the level of the highest electrode structure. The silicide is then selectively etched to allow for subsequent exposure of the gate electrodes. Preferably, the silicide will be etched until it is no higher than the lowest gate electrode. The etchant must be selective such that the silicide is etched faster than the electrode cap, so that a sufficient portion of every electrode remains to allow for subsequent contact upon completion of the etching process. Once the silicide has been etched to its desired height, the device can be masked to protect the areas where silicide is desired. The silicide can then be patterned, such that the remaining, unwanted, silicide can then be etched. This will typically leave silicide over the source region and the drain region. Preferably, the silicide will extend over the isolation regions to form larger source/drain contact regions. Subsequently, standard processes can be employed to complete formation of the desired device.
Although silicide is preferred, it would also
Hsu Sheng Teng
Sakiyama Keizo
Chaudhari Chandra
Krieger Scott C.
Rabdau Matthew D.
Ripma David C.
Sharp Laboratories of America Inc.
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