Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1990-01-02
2001-05-01
Nelson, Peter A. (Department: 3641)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S059000, C438S167000
Reexamination Certificate
active
06225178
ABSTRACT:
FIELD OF INVENTION
The present invention pertains to integrated circuit technology and particularly to radiation-hardened very-large-scale integrated (VLSI) circuit technology. More particularly, the invention pertains to metal oxide semiconductor (MOS) circuitry.
BACKGROUND OF THE INVENTION
The related art technology, radiation-insensitive complementary metal oxide semiconductor (RICMOS), involves radiation hardened field oxide which results in poor topography making it impractical for adequate submicron line patterning needed for state-of-the-art VLSI technology.
The part of an MOS structure Most sensitive to ionizing radiation is the oxide insulating layer. When the radiation passes through the oxide, the energy deposited creates electron/hole pairs. The radiation-generated electrons are more mobile than the holes and are swept out of the oxide in about a picosecond. During the moment, a fraction of the electrons and holes recombine. The amount of recombination depends on the applied field and the kind and energy of the incident particle. The holes that escape the initial recombination are relatively immobile and remain near their point of generation, thereby causing negative voltage shifts in the electrical characteristics of the MOS device. But over a longer period of time, exceeding one second, the holes undergo a rather anomalous stochastic hopping transport through the oxide in response to any electric fields present. This hole transport process gives rise to a short-term, transient recovery in the voltage shift. When the holes reach the SiO
2
interface (for positive gate bias), some of them are captured in long-term trapping sites, and cause a remnant negative voltage shift that is not sensitive to the silicon surface potential, which can last from hours to years. This long-term radiation-induced voltage shift is a common form of radiation damage in MOS devices. The long-term trapping of holes (i.e., a net positive charge in the oxide layer) near the interface, as well as subsequent anealing of them, is sensitive to the processing of the oxide and to field and temperature. This effect generally dominates other radiation damage processes in MOS structures.
Much effort in the related art has been directed toward reducing and controlling oxide positive charge trapping. Early radiation-insensitive MOS circuits had ionic contaminants in the gate oxide materials to alter and improve the oxide properties under radiation. Later on, MOS device fabrication techniques and process controls in the related art improved, and thus the hardening techniques that relied on impurity addition to the oxide fell out of favor (at least for gate oxide). Radiation hardening then concentrated on the primary source of the radiation-generated oxide positive charge (i.e., the trapped hole). A hole trap designates normally neutral oxide defects that can capture holes and retain then for long periods of time.
Radiation-induced generation and trapping of holes is a problem in both gate oxide and field or silicon oxide of MOS devices. Field oxides are typically about an order of magnitude thicker than gate oxides. The properties of field oxides are not as well controlled as those of gate oxides. In the related art, field oxides may be produced by processes such as chemical vapor deposition (CVD), not used for gate oxides. Threshold voltage changes due to radiation are proportional to the square of the oxide thickness. For instances a relatively small radiation dose causes a significant change in threshold voltage in a parasitic field oxide field effect transistor (FET). Greater oxide thickness also results in smaller electric fields in the oxides. Smaller fields reduce charge yield and enhance both hole capture and electron/hole recombination at the hole traps. Greater oxide thickness also increases the charge-generation volume and the distance that both holes and electrons must travel to escape the oxide, which in turn enhances trapping and recombination. The net result is that space and recombination effects begin to dominate the voltage threshold change of field oxides at doses of a few Krad (SiO
2
), two or three orders of magnitude below the levels of radiation that typically cause such effects in the thinner gate oxides. Both the increase in oxide thickness and the decrease in the oxide field also greatly increase the time scale of hole transport through the oxide. Hence, substantial hole transport may take place in a field oxide for thousands of seconds after being subject to radiation.
In clean, thermally grown oxides on silicon, the long-term charge trapping responsible for the voltage threshold change is dominated by the trapping of holes.
The effect of radiation on field oxide isolation usually in MOS transistor structures is of concern here. A thick oxide is used to electrically isolate transistors from one another and to terminate the active channel within a given transistor and thus define the channel width. In a radiation environment, the field oxide traps have sore charge than the gate oxide. For oxide isolation over p-type substrates (i.e. for n-channel isolation), the threshold voltage under thick oxide regions can be reduced significantly by radiation to the extent of dropping below zero volts. Then isolation becomes ineffective and leakage currents increase. One leakage current path may be an “end-around” leakage between the source and the drain of a transistor. Another leakage current path may be between the n-channel source and the n-substrate (in bulk p-well CMOS technology; but in an n-well technology the leakage path would between the n-channel source and the n-well).
The maintenance of isolation between adjacent devices and between the source and drain of n-channel transistors is a major factor in the design of radiation-hardened circuits. When subject to radiations the field oxide tends to have a large buildup of trapped holes that can lead to an inversion of the surface over p-type regions. Large threshold voltage shifts are possible and tend to be proportional to oxide thicknesses. The buildup of trapped holes leads to a degradation of isolation between and within n-channel devices, and can cause circuit failure at relatively low radiation levels (1-5 krads).
Various approaches have been attempted to remove the detrimental effects of radiation on oxides of the transistors. A channel stop or guardband has been used to provide isolation between adjacent devices. However, the threshold voltage of this region is usually not sufficient to prevent inversion in a radiation environment, and the design does not provide sufficient protection against radiation-induced leakage between the source and the drain within an n-channel transistor. Guardbands require additional process steps and additional space in layout for a radiation-hardened circuit.
Another approach uses polysilicon only as a gate electrode which results in greatly reduced packing density oxide since the polysilicon cannot be effectively used as an interconnect layer. The use of polysilicon field shield is not necessarily fully effective in an ionizing radiation environment to prevent source-to-drain leakage.
One other approach utilizes closed gate structures such as closed complementary logic (C
2
L). There is no leakage path between the source and drain with the C
2
L layout. However, such structure is very inefficient in its use of silicon area, particularly for multiple-input gates.
Still another approach attempts to maintain isolation in a radiation environment by altering the processing to produce a radiation-hardened field oxide. This approach adds significant process complexity.
Various tradeoffs by the various approaches noted above have pointed to an approach using a thin field oxide between the source and the drain and a thick field oxide elsewhere to isolate the transistor from rest of the circuit. This layout is combined with an epitaxial substrate.
SUMMARY OF THE INVENTION
The present invention is a version of the hardened reduced bird's beak (HRBB) process based on manufacturable, thermal oxidation
Rahn Curtis H.
Randazzo Todd A.
Shaw Gordon A.
Yue Cheisan
Fredrick Kris T.
Honeywell Inc.
Nelson Peter A.
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