Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Patent
1998-08-07
2000-03-21
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
G06F 112
Patent
active
060414189
ABSTRACT:
A flag generating circuit that uses a feedback mechanism to set or reset a flag associated with two systems with asynchronous clocks is provided. Upon receipt of a set flag (or reset flag) signal, the circuit immediately isolates the signal after setting (or resetting) the flag to prevent race conditions between the systems. The clock associated with the setting system is synchronously started when waiting to set the flag and synchronously stopped when waiting for the flag to be reset. The clock associated with the resetting system is synchronously started when waiting to reset the flag and synchronously stopped when waiting for the flag to be set. Accordingly, the flag generating circuit provides a race free and technology independent flag generating circuit capable of setting and resetting flags associated with asynchronous
REFERENCES:
patent: 5311475 (1994-05-01), Huang
patent: 5315184 (1994-05-01), Benhamida
patent: 5336938 (1994-08-01), Sywyk
patent: 5355113 (1994-10-01), McClure
patent: 5781802 (1998-07-01), Cassetti
Chen Feng
Kolagotla Ravi K.
Ly Le T.
Mo Jiancheng
Srinivas Hosahalli R.
Heckler Thomas M.
Lucent Technologies - Inc.
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