Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-22
2004-12-14
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S330000, C257S331000, C257S332000, C438S212000, C438S268000, C438S267000, C438S213000
Reexamination Certificate
active
06831329
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to Integrated Gate Bipolar Transistors (IGBTs) and, more particularly, to quick punch through IGBTs.
DESCRIPTION OF THE RELATED ART
IGBTs can be constructed in a variety of cell configurations, such as, for example closed cell geometries and trench stripe cells. For simplicity, the structure of a typical IGBT is hereinafter discussed with reference to a stripe cell configuration IGBT. Referring to
FIG. 1
, an IGBT
10
having a stripe cell configuration is shown. Each cell of IGBT
10
includes epitaxial layer
12
in which two source stripes
14
and
16
are formed. The source stripes
14
,
16
are surrounded within the epitaxial layer
12
by a base stripe
18
. A portion of the base stripe
18
separates or lies between the source stripes, and is referred to as the body stripe
20
.
The epitaxial layer
12
includes a lightly-doped drift region
22
that is disposed over a heavily doped buffer region
24
. The heavily doped buffer region is disposed over a P-type collector region
25
. Gate insulating stripes
26
and
28
, typically of silicon dioxide, cover the top of epitaxial layer
12
. Gate conductive stripes
30
and
32
, typically of heavily doped polysilicon, cover insulating stripes
26
and
28
, and form a gate electrode (not referenced). Gate conductive stripes
30
and
32
overlie corresponding channel stripes (not referenced) on opposite sides of the base stripe. Another insulating layer (not referenced) covers the gate stripes
30
and
32
. A metal layer contacts the source stripes
14
,
16
and body stripe
20
. On the side of IGBT
10
that is opposite or underlying gate stripes
30
and
32
, an emitter electrode
34
is formed.
IGBTs are widely used in switching applications, such as, for example, uninterruptible power supplies (UPS), switched mode power supplies, power factor correction circuits, and motor drive circuits. Accordingly, punch through (PT) IGBTs are typically designed with the goals of reducing electromagnetic interference (EMI) and reducing collector voltage overshoot. In order to reduce EMI and collector voltage overshoot, the punch through of the depletion region
22
into the buffer region
24
must be prevented at the bus or switching voltage used in the particular application. Preventing the punch through, in turn, is accomplished by manipulating the dopant concentration in and the thickness of drift region
22
. What is referred to as “soft turn off” is only accomplished through this relatively complicated balancing of drift region thickness and dopant concentration. This balancing produces an PT IGBT that is optimized for a specific operating bus voltage and current density, rather than an IGBT that is capable of operating with relatively optimally reduced EMI and collector voltage overshoot across a range of operating parameters.
Even PT IGBTs that are optimized for a particular set of operating parameters have certain undesirable characteristics. For example, conventional IGBTs have a relatively large and undesirable collector voltage overshoot at punch through. Further, the gate voltage (Vg) of a conventional IGBT may drop below zero volts at punch through, then recharge and undesirably turn the PT IGBT back on thereby delaying the turn off time of the PT IGBT. Moreover, conventional IGBTs have a current fall di/dt that is relatively large, substantially uncontrolled, independent of the gate resistance of the external drive circuit, and which contributes to an increased level of EMI.
Therefore, what is needed in the art is an IGBT that reduces EMI and collector voltage overshoot relative to a conventional PT IGBT.
Furthermore, what is needed in the art is an IGBT that reduces the need to perform the complicated balancing of the drift region thickness and dopant concentration in order to reduce EMI and collector voltage overshoot.
Still further, what is needed in the art is an IGBT that maintains the gate voltage at a level sufficient to prevent the IGBT from turning back on, thereby reducing the turn off delay time.
Moreover, what is needed in the art is an IGBT that controls the current fall di/dt at and following punch through.
SUMMARY OF THE INVENTION
The present invention provides a quick punch through integrated gate bipolar transistor (QPT IGBT).
The invention comprises, in one form thereof, a quick punch through IGBT having a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or above the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.
An advantage of the present invention is turn-off delay time is reduced relative to a conventional PT IGBT.
Another advantage of the present invention is that collector voltage overshoot is substantially reduced relative to the overshoot in a conventional PT IGBT, alleviating the need for snubber circuits.
A further advantage of the present invention is that the rate of change of IGBT current during turn off is reduced, thereby reducing electromagnetic interference.
A still further advantage of the present invention is that turn-off losses are reduced with decreasing bus voltages.
REFERENCES:
patent: 5346835 (1994-09-01), Malhi et al.
patent: 5510634 (1996-04-01), Okabe et al.
patent: 5932897 (1999-08-01), Kawaguchi et al.
patent: 6208185 (2001-03-01), John et al.
patent: 6242787 (2001-06-01), Nakayama et al.
patent: 6259136 (2001-07-01), Kawaguchi et al.
patent: 6482681 (2002-11-01), Francis et al.
patent: 2002/0048855 (2002-04-01), Matsudai et al.
patent: 2003/0042575 (2003-03-01), Takahashi et al.
Dolny Gary M.
Gladish Jon
Lange Douglas Joseph
Muraleedharan Shenoy Praveen
Rinehimer Mark L.
Erdem Fazli
Fairchild Semiconductor Corporation
FitzGerald Esq. Thomas R.
Roach, Esq. Laurence S.
Tran Minhloan
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