Queue management mechanism which allows entries to be processed

Details Queue management mechanism which allows entries to be processed Queue management mechanism which allows entries to be processed

1995-03-31

1997-09-09

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711104, 711105, 711158, 395877, G06F 1314, G06F 1200, G11C 800

Patent

active

056664940

ABSTRACT:
A memory subsystem includes a posted write buffer for dynamic random access memories (DRAMs). The posted write buffer includes read around logic to enable read accesses to be processed in advance of posted writes. Data are transferred from the posted write buffer to the DRAMs on a general first-in/first out basis; however, in order to take advantage of page mode operation, posted writes having the same row address as a current memory access are given priority over other posted writes such that the posted writes may be written out of order. In addition, comparisons are made between addresses of incoming read accesses and addresses of posted writes in order to expedite the transfer of posted writes having the same row addresses to memory in order to service the incoming read accesses on a timely basis. An improved write access buffer permits posted writes to be transferred to the DRAMs out of order without losing track of the skipped posted writes.

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"Fast Data Access of DRAMs by Utilizing a Queued Memory Command Buffer", IBM Technical Disclosure Bulletin, vol. 35, No. 7, pp. 63-66. Dec. 1992.

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