Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-09-30
2002-11-19
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S537000, C324S1540PB
Reexamination Certificate
active
06483327
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to inspection of integrated circuits, and more particularly to inspection of integrated circuits using photo-emissions.
BACKGROUND OF THE INVENTION
The semiconductor industry has seen tremendous advances in technology in recent years, permitting dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Typically, dies contain a bonding pad which makes the electrical connection to the semiconductor package. To shorten the electrical path to the pad, another packaging technology called flip-chip packaging is employed, where the bonding pads were moved to the side of the die nearest the transistors and other circuit devices formed in the die. Connection to the package is made when the chip is flipped over and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump on a pad connects to a corresponding package inner lead. The packages which result are lower profile and have lower electrical resistance and a shortened electrical path. The plurality of ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. The packages are occasionally referred to as “Ball Grid Array” (BGA) or “Area Grid Array” packages.
FIG. 1
is a cross-sectional view of an example BGA device
10
. The device
10
includes an integrated circuit
12
mounted upon a larger package substrate
14
. Substrate
14
includes two sets of bonding pads: a first set of bonding pads
16
on an upper surface adjacent to integrated circuit
12
and a second set of bonding pads
18
arranged in a two-dimensional array across an underside surface. Integrated circuit
12
includes a semiconductor substrate
20
having multiple electronic components formed within a circuit layer
22
upon a front side surface of semiconductor substrate
20
during wafer fabrication. The back side surface
23
remains exposed after the device
10
is formed. The electronic components are connected by electrically conductive interconnect lines to form an electronic circuit. Multiple I/O pads
24
are also formed within circuit layer
22
. I/O pads
24
are typically coated with solder to form solder bumps
26
.
The integrated circuit is attached to the package substrate using the controlled collapse chip connection method, which is also known as the C4® or flip-chip method. During the C4 mounting operation, solder bumps
26
are placed in physical contact with corresponding members of the first set of bonding pads
16
. Solder bumps
26
are then heated long enough for the solder to reflow. When the solder cools, I/O pads
24
of integrated circuit
12
are electrically and mechanically coupled to the corresponding members of the first set of bonding pads
16
of the package substrate. After integrated circuit
12
is attached to package substrate
14
, the region between integrated circuit
12
and package substrate
14
is filled with an under-fill material
28
to encapsulate the C4 connections and provide additional mechanical benefits.
Package substrate
14
includes one or more layers of signal lines that connect respective members of the first set of bonding pads
16
and the second set of bonding pads
18
. Members of the second set of bonding pads
18
function as device package terminals and are coated with solder, forming solder balls
30
on the underside surface of package substrate
14
. Solder balls
30
allow BGA device
10
to be surface mounted to an ordinary PCB. During PCB assembly, BGA device
10
is attached to the PCB by reflow of solder balls
30
just as the integrated circuit is attached to the package substrate.
The C4 mounting of integrated circuit
12
to package substrate
14
prevents physical access to circuit layer
22
for failure analysis and fault isolation. Thus, new approaches that are efficient and cost-effective are required.
It is well known that CMOS transistors emit photons during a state change, for example, switching the gate of a transistor. Photons are emitted from transistors at pn junctions, for example. These transient events occur on time scales that are less than 100 ps. Thus, in order to record these events, a very fast detector is required. In addition, a very sensitive detector is required for observing very weak emissions through the backside of the semiconductor because of the absorption losses in the silicon substrate. Another aspect of the emission analysis is to spatially resolve the emissions. It is desired to detect emissions from a single transistor where the device dimensions may be sized less than a micron. Therefore, an apparatus and method that provides fast and cost effective spatially and temporally resolved photoemission analysis of semiconductor circuits is desirable.
Various approaches to picosecond imaging circuit analysis (PICA) have been implemented. For example, one apparatus uses a cooled microchannel plate photomultiplier tube (MCP-PMT), with a position sensitive resistive anode to simultaneously image and time-resolve optical emission from individual FETs in submicron CMOS circuits. However, the MCP-PMT is relatively inefficient for wavelengths in the range of 900-1300 nm. That is, the MCP-PMT is not very sensitive to light in this range.
SUMMARY OF THE INVENTION
In various embodiments, methods and systems are provided for time resolved photoemission microscopy for an integrated circuit. In one embodiment an apparatus is provided for analyzing an integrated circuit to which test signals are applied. The apparatus includes a microscope having an objective lens forming a focal plane arranged to view the integrated circuit, and an aperture element having an aperture optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A position-sensitive avalanche photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5412328 (1995-05-01), Male et al.
patent: 5451863 (1995-09-01), Freeman
patent: 5550479 (1996-08-01), Wakana et al.
patent: 5631571 (1997-05-01), Spaziani et al.
patent: 5663652 (1997-09-01), Freeman
Zappa, F., Lacaita, A., Cova, S., and Lovati, P.,Counting, Timing, and Tracking with a Single-Photon Germanium Detector,1996, Optical Society of America, pp. 59-61.
EG&G Optoelectroncs,Silicon APD Arrays Quadrant and Linear 400nm to 1100nm,Sep. 1999, pp. 1-3.
Kash, J., Tsang, J., Knebel, D., and Vallett, D.,Non-invasive Backside Failure Analysis of Integrated Circuits by Time-dependent Light Emission: Picosecond Imaging Circuit Analysis,Nov. 1998, pp. 1-6.
Knebel, D., Sanda, P., McManus, M., Kash, J., Tsang, J., Vallett, D., Huisman, L., Nigh, P., Rizzolo, R., Song, P., and Motika, F.,Diagnosis and Characterization of Timing-Related Defects by Time-Dependent Light Emission,pp. 1-7.
Quantar Technology, Inc.,Domestic Price List Series 2600 Imaging Photon Detector Systems,Apr., 1997, pp. 1-3.
EG&G Optoelectronics,X-Y Sensors and Quadrant Detectors,Sep., 1999, pp. 1-3.
Barton, D., Tangyunyong, P., Soden, J., Liang,
Birdsley Jeffrey D.
Bruce Michael R.
Bruce Victoria J.
Davis Brennan V.
Goruganthu Rama R.
Advanced Micro Devices , Inc.
Hollington Jermele
Sherry Michael
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