Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2001-05-21
2003-06-24
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S669000, C257S676000
Reexamination Certificate
active
06583499
ABSTRACT:
CROSS RELATED APPLICATION
This application claims the benefit priority of Taiwan application serial No. 89125445, filed Nov. 30, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a quad flat non-leaded package. More particularly, the invention relates to the bonding structure of a quad flat non-leaded package.
2. Description of the Related Art
As the era of information technology progresses, the transmission and processing of information and documents are increasingly performed via sophisticated electronic products. Accompanying the progress of technology, many commercial products with more convenient features have been promoted, such as mobile phones, computers, audio-video articles, etc. In such a context, various high-density packaging structures thus are manufactured, such as chip scale packages (CSP), multi-chip modules (MCM), etc.
Among these various packaging structures, the quad flat non-leaded package (QFN) has been developed by the Matsusita company. The quad flat non-leaded package (QFN) usually is a leadframe-based chip scale package (CSP). Advantageously, the conductor traces of the non-leaded chip scale package (CSP) are short, which reduces the deterioration of the transmitted signal. Such a packaging structure is conventionally used to package low pin count semiconductor elements.
FIG. 1
shows a conventional quad flat non-leaded package (QFN) structure. The conventional quad flat non-leaded package
100
comprises a chip
110
, a leadframe
130
, and a molding compound
160
. The chip
110
has an active surface
112
and a corresponding back surface
114
, wherein the active surface
112
of the chip
110
comprises a plurality of bonding pads
116
. The leadframe
130
comprises a die pad
140
and a plurality of leads
150
, wherein the die pad
140
has an upper surface
142
and a corresponding lower surface
144
, and each of the leads also has an upper surface
152
and a corresponding lower surface
154
. Within the package structure, the chip
110
is adhered by the back surface
114
thereof to the upper surface
142
of the die pad
140
and, through the bonding wires
170
, the bonding pads
116
are respectively connected to the leads
150
. The molding compound
160
encapsulates the chip
110
, the bonding wires
170
, the upper surfaces
152
of the leads
150
, and the upper surface
142
of die pad
140
while exposing the lower surfaces
154
of the leads
150
and the lower surface
144
of the die pad
140
.
The quad flat non-leaded package (QFN)
100
is further mounted upon a printed circuit board
180
that has a plurality of contact nodes
182
and a ground contact node
184
located at the center of the contact nodes
182
. Via a reflow process, bonding materials
192
and
194
respectively connect the lower surface
154
of the leads
150
to the contact nodes
182
and the lower surface
144
of the die pad
140
to the ground contact node
184
of the printed circuit board
180
.
FIG. 1A
shows an upward view of the quad flat non-leaded package of
FIG. 1
in which the die pad and the leads are exposed through the molding compound. In the conventional quad flat non-leaded package (QFN)
100
, the lower surface
144
of the die pad
140
is square-shaped and is substantially large. As a result, when the bonding material
194
underneath the die pad
140
is reflowed, the generated surface tension on the bonding material
194
causes the die pad
140
to drift above the ground contact node
184
. The deviation of the position of the die pad may cause an inaccurate connection of the leads
150
to the contact nodes
182
of the printed circuit board
180
and therefore decrease the quality of the electrical connections.
SUMMARY OF THE INVENTION
An aspect of the invention is to provide a quad flat non-leaded package and a leadframe structure for a quad flat non-leaded package in which the quality of the electrical bonding between the quad flat non-leaded package (QFN) and the printed circuit board is improved.
Another aspect of the invention is to provide a quad flat non-leaded package and a leadframe structure for a quad flat non-leaded package wherein the leads of the quad flat non-leaded package (QFN) can be accurately connected to the contact nodes of the printed circuit board.
To attain the foregoing and other objectives, the present invention provides a quad flat non-leaded package (QFN) that, according to a preferred embodiment, comprises: a die pad having a first upper surface and a corresponding first lower surface, wherein the first lower surface of the die pad has a plurality of interlacing slots, each of the interlacing slots uniformly extending to the edges of the lower surface of the die pad to define a plurality of island-like blocks; a plurality of leads disposed at the periphery of the die pad, wherein each of the leads respectively has a second upper surface and a corresponding second lower surface substantially coplanar with the surface of the island-like blocks; a chip having an active surface with a plurality of bonding pads thereon respectively connected to the leads and a corresponding back surface adhered onto the first upper surface of the die pad; and a molding compound encapsulating the chip, the second upper surfaces of the leads, and the first upper surface of the die pad while exposing the surface of the island-like blocks and the second lower surfaces of the leads.
To attain the above and other objectives, the invention further provides a quad flat non-leaded package (QFN) suitable to be arranged on a printed circuit board, the printed circuit board comprising a plurality of contact nodes and a ground contact node disposed at the center of the contact nodes. The quad flat non-leaded package (QFN) suitable to be arranged on the printed circuit board, according to another embodiment of the present invention, comprises: a die pad having a first upper surface and a corresponding first lower surface, wherein the first lower surface of the die pad has a plurality of interlacing slots, each of the interlacing slots respectively extending to the edges of the lower surface of the die pad, thereby forming a plurality of island-like blocks; a plurality of leads disposed at the periphery of the die pad, wherein each of the leads respectively has a second upper surface and a corresponding second lower surface substantially coplanar with the surface of the island-like blocks; a chip having an active surface with a plurality of bonding pads thereon respectively connected to the leads and a corresponding back surface adhered onto the first upper surface of the die pad; and a molding compound encapsulating the chip, the second upper surface of the plurality of leads, and the first upper surface of the die pad while exposing the surface of the island-like blocks and the second lower surfaces of the leads. The second lower surface of each of the leads is respectively connected to the contact nodes of the printed circuit board through a plurality first bonding materials, while the islands-like blocks are respectively connected to the ground contact node through a plurality of second bonding materials to provide electric and heat dissipation paths.
To attain the above and other objectives, the invention further provides a leadframe suitable for use in a quad flat non-leaded package (QFN). The leadframe, according to another embodiment of the present invention, comprises: a die pad having a first upper surface and a corresponding first lower surface, wherein the first lower surface of the die pad has a plurality of interlacing slots, each of the interlacing slots extending uniformly to the edges of the lower surface of the die pad to form a plurality of island-like blocks; and a plurality of leads disposed at the periphery of the die pad, wherein each of the leads respectively has a second upper surface and a corresponding second lower surface substantially coplanar to the surface of the island-like blocks.
In an example of the present invention, the die pad is substantially square and the
Her Tzong-Dar
Huang Chien-Ping
Lewis Monica
Siliconware Precision Industries Co. Ltd.
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