Quad aware locking primitive

Details Quad aware locking primitive Quad aware locking primitive

2011-07-12

2011-07-12

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Access locking

C710S240000, C710S260000

Reexamination Certificate

active

07979617

ABSTRACT:
A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.

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