Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2006-05-30
2008-08-12
Cho, James H (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S093000, C327S199000
Reexamination Certificate
active
07411413
ABSTRACT:
The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.
REFERENCES:
patent: 5444404 (1995-08-01), Ebzery
patent: 5719878 (1998-02-01), Yu et al.
patent: 6073260 (2000-06-01), Kurita
patent: 10-112635 (1998-04-01), None
patent: 10-267994 (1998-10-01), None
patent: WO 2004/038917 (2004-05-01), None
Nishibori Masakazu
Shimazaki Yasuhisa
Cho James H
Miles & Stockbridge P.C.
Renesas Technology Corp.
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