Pseudo-static semiconductor memory cell

Details Pseudo-static semiconductor memory cell Pseudo-static semiconductor memory cell

1978-07-19

1980-01-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365154, 365222, 307238, G11C 1140

Patent

active

041842081

ABSTRACT:
An MOS memory cell of the pseudo static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series transistors connecting storage nodes to a supply voltage. The storage nodes are connected to complimentary data lines by a pair of coupling transistors controlled by a word address. The series transistors are turned on in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. The series transistors are not used for read or write operations.

REFERENCES:
patent: 3949383 (1976-04-01), Askin
patent: 3949385 (1976-04-01), Sonoda
patent: 4122541 (1978-10-01), Uchida

Affiliated with

Also associated with

Rating

Pseudo-static semiconductor memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pseudo-static semiconductor memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pseudo-static semiconductor memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1030717