Pseudo random sequence generation

Details Pseudo random sequence generation Pseudo random sequence generation

1986-11-07

1988-07-05

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, 307445, G11C 1140, G11C 1300

Patent

active

047559691

ABSTRACT:
Circuits for generating sequences of pseudo random binary digits wherein the circuit can be easily programmed to change the sequence. The sequences are obtained by modulo-2 addition of digits retrieved from storage in Random Access Memories (RAMs). Two or more Read counters identify separate addresses in the RAMs from which the digits are retrieved. A Write counter points into an address in all of the RAMs where each current sequence bit is stored as it is formed at the output of an Exclusive-Or gate which performs the modulo-2 addition. Each of the Read counters lags the Write counter by a different and programmable amount and these lags determine which sequence is generated.

REFERENCES:
patent: 4596002 (1986-06-01), Chan et al.
patent: 4600846 (1986-07-01), Burrows

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