Pseudo-NMOS logic circuits with negligible static current during

Details Pseudo-NMOS logic circuits with negligible static current during Pseudo-NMOS logic circuits with negligible static current during

1994-01-18

1995-11-14

Westin, Edward P.

Electronic digital logic circuitry

With test facilitating feature

326 33, 327530, 324522, H03K 1900, H03K 1716

Patent

active

054670268

ABSTRACT:
A modified pseudo-nMOS logic gate for use in systems in which quiescent current testing is desired. The load transistor of each pseudo-nMOS gate is controlled by a two-input load control gate. One input of the load control gate is connected to a global test signal and the second input of the load control gate is connected to the output of the pseudo-nMOS gate. In normal operation, the global test signal is logically true, and the load control gate has no effect on the pseudo-nMOS gate. During quiescent current testing, the global test signal is logically false and the output of the load control gate is determined by the logical output of the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically true, the load control gate has no effect on the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically false, the load control gate turns off the load transistor so that no static current flows through the load transistor. As a result, the logical state of the pseudo-nMOS gate is preserved, but the modified gate draws negligible static current during quiescent current testing.

REFERENCES:
patent: 4549101 (1985-10-01), Sood
patent: 5192881 (1993-03-01), Martin

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