Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-12
2003-12-30
Lebentritt, Micael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S240000
Reexamination Certificate
active
06670232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a capacitor.
2. Description of the Background Art
A DRAM (dynamic random access memory) is one of semiconductor memory devices for allowing random input/output of stored data. A DRAM generally has a memory cell array section serving as a region for accumulating a large amount of stored data, and a peripheral circuit section responsible for I/O operations to and from outside.
The memory cell array section includes a number of memory cells arranged in a matrix and covers a large area on a semiconductor chip. Each memory cell is capable of accumulating unit memory data. The memory cell generally includes one MOS (metal oxide semiconductor) transistor and one capacitor connected to the MOS transistor. The memory cell of this type is called as a one-transistor one-capacitor cell. The one-transistor one-capacitor memory cell has a simple configuration and hence, can be suitably adopted for increasing density in the memory cell array. In view of this, the one-transistor one-capacitor memory cell is widely used in mass DRAMs.
FIG. 12
illustrates an exemplary structure of a capacitor constituting the one-transistor on-capacitor memory cell. As illustrated in
FIG. 12
, a first interlayer insulating film
2
including silicon oxide is provided on a semiconductor substrate
0
that may be a silicon substrate, for example. The first interlayer insulating film
2
includes a plug
1
formed therein. The plug
1
includes titanium nitride and penetrates the first interlayer insulating film
2
. Further, a second interlayer insulating film
3
including silicon oxide is stacked to cover the plug
1
and the first interlayer insulating film
2
.
A lower electrode
4
including platinum is connected to the plug
1
. The lower electrode
4
penetrating the second interlayer insulating film
3
stands upright on the plug
1
, slightly cutting into the plug
1
.
A dielectric film
7
including a high dielectric constant material such as barium strontium titanate is provided to cover the lower electrode
4
and the second interlayer insulating film
3
. Further, an upper electrode
8
including platinum is provided for covering the dielectric film
7
. The elements described so far constitute a capacitor.
Further, a third interlayer insulating film
9
is provided to cover the upper electrode
8
. The third interlayer insulating film
9
provided over the capacitor includes aluminum interconnection formed therein (not illustrated). Still further, the semiconductor substrate
0
includes an element isolating oxide film, an active region, a MOS transistor connected to the plug
1
, and the like each formed therein (none of which are illustrated).
For the purpose of increasing density in the memory cell array, an effort has been underway to shrink the dimension of a capacitor for constituting each memory cell. As seen from
FIG. 12
, a capacitor has been of an elongated structure, for example, thus allowing shrinkage of the capacitor in dimension without reducing capacitance thereof. According to this structure, even when areas of upper and bottom surfaces of the lower electrode
4
are respectively reduced for the purpose of shrinkage, a lateral area of the same can still be enlarged. Hence, there occurs no reduction in contact area between the lower electrode
4
and the dielectric film
7
.
However, it has been difficult to form the lower electrode
4
into an elongated structure. That is, due to small pattern width, inclination of a pattern may be caused in a photoresist by merely performing ordinary photolithography and etching. Alternatively, even if there occurs no pattern inclination, a resultant width of the lower electrode
4
does not comply with that of a pattern. In this case, the lower electrode
4
may extend widely in width.
As a countermeasure against this problem, a damascene process has been suggested for forming the lower electrode
4
.
FIGS. 13 and 14
illustrate in part the steps of the damascene process.
First, the plug
1
, and the first and second interlayer insulating films
2
and
3
are provided on the semiconductor substrate
0
. Further provided on the upper surface of the second interlayer insulating film
3
is a mold
10
including a silicon oxide film, for example. Utilizing lithography and etching, an opening OP
2
for forming the lower electrode
4
is defined in the mold
10
(FIG.
13
). As illustrated in
FIG. 14
, platinum is thereafter deposited by sputtering, for example. Then a film
4
c
defined over the upper surface of the mold
10
is removed by the technique such as CMP (chemical mechanical polishing). Next, the mold
10
is removed. Following this, the dielectric film
7
, the upper electrode
8
, and the third interlayer insulating film
9
are provided, thus completing the capacitor as illustrated in FIG.
12
.
Following the damascene process as described, reduction in pattern width of a photoresist will not occur, thus preventing the foregoing problem. Hence, the lower electrode
4
can be formed into an elongated shape.
However, the damascene process still has a problem. That is, the redundant film
4
c
is inevitably defined over the mold
10
, necessitating the step of removing the same. Further, when a material for forming an electrode is deposited by sputtering, for example, it is quite difficult to deposite the same only in the opening OP
2
. In contrast, the reduced amount of material may cause the problem that the opening OP
2
cannot be filled to a sufficient degree. As a result, the lower electrode
4
cannot be properly formed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of omitting the steps of forming a redundant film and removing the same.
According to a first aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) through (e). The step (a) provides an element. The step (b) provides a conductive layer. The step (c) provides an insulating layer. The step (d) defines an opening. The step (e) brings the conductive layer to a conducting state for providing a conductive material in the opening. In the step (a), the element is arranged in a main surface of a semiconductor substrate. In the step (b), the conductive layer is arranged above the main surface of the semiconductor substrate through an interlayer insulating film. In the step (c), the insulating layer is arranged on the conductive layer. The opening penetrates the insulating layer and the conductive layer. The conductive material is electrically connected to the element.
The conductive layer is brought to a conducting state and the conductive material is provided in the opening. Therefore, the conductive material is formed with reliability in the opening. Further, the conductive layer holds the insulating layer provided thereon. Therefore, it is possible to avoid the conductive material from being deposited over the conductive layer. As a result, the method is allowed to omit the steps of forming a redundant film and removing the same.
According to a second aspect of the present invention, the method of manufacturing a semiconductor device includes the following steps (a) through (e). The step (a) provides an element. The step (b) provides a first layer. The step (c) provides a second layer. The step (d) defines an opening. The step (e) selectively provides a conductive material in the opening by CVD. In the step (a), the element is arranged in a main surface of a semiconductor substrate. In the step (b), the first layer is arranged above the main surface of the semiconductor substrate through an interlayer insulating film. In the step (c), the second layer is arranged on a surface of the first layer. The opening penetrates both the first and second layers. The conductive material is electrically connected to the element. The conductive material is selectively deposited more on the first la
Lebentritt Micael S.
Renesas Technology Corp.
Smith Brad
LandOfFree
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