Progressive random access scan circuitry

Details Progressive random access scan circuitry Progressive random access scan circuitry

2006-09-25

2010-02-16

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07665001

ABSTRACT:
A scan cell is described for testing an integrated circuit. The scan cell may include circuitry adapted to operate in a non-test mode as a storage element and adapted to operate as a static random access memory (SRAM) cell in a test mode. For example, the circuitry may include one or more pass transistors and a flip flop. The scan cell may be one of a plurality of addressable scan cells in one or more grids for testing the integrated circuit. For example, the scan cells may be arranged in a single grid or may be partitioned into two or more grids. The scan cell may be used for reliability testing or for performance testing. The PRAS cell for performance testing may be staged, with a first pattern applied and then a second pattern applied. For example, one section of the scan cell may operate using a clock cycle of Φ1and another section of the PRAS cell may operate using a clock cycle of Φ2which is different from Φ1.

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Michael L. Bushnell et al., “Essentials of Electronic Testing For Digital, Memory and Mixed-Signal VLSI Circuits,” Kluwer Academic Publishers; 2000; pp. Title p. 2, Table of Contents (8).
Dong Hyun Baik, et al., “Random Access Scan: A solution to test power, test data volume and test time,” 17thInternational Conference on VLSI Design; 2004; (6 pages).
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