Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2002-08-30
2004-03-30
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S039000, C326S041000, C716S030000, C365S189011, C365S189070, C365S230080, C711S170000
Reexamination Certificate
active
06714041
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the area of programmable logic devices. In particular, the present invention relates to a method and apparatus for reprogramming a complex programmable logic device (CPLD) without halting system operation.
2. Discussion of Related Art
Reprogrammable integrated circuits (ICs) provide a great deal of flexibility and control to circuit designers. For example, an in-system programmable (ISP) device can be programmed while installed in an electronic system (i.e., mounted on a circuit board with other components), thereby allowing modifications or upgrades to be performed on a completed product without replacing any hardware. In a complex programmable logic device (CPLD), this reprogrammability is typically provided by an EEPROM (electrically erasable programmable read-only memory) array.
FIG. 1
shows an electronic system
190
that includes a conventional CPLD
100
. CPLD
100
comprises a configuration control circuit
110
, an EEPROM array
120
, and a configurable logic space
130
that includes a programmable interconnect matrix
131
and macrocells
132
a
-
132
d
. Configuration control circuit
110
is coupled to receive an instruction INST and provide in response a configuration control signal CFG_CTRL that controls the loading of a set of configuration data CFG_DAT into EEPROM array
120
. This in turn places I interconnect matrix
131
and macrocells
132
a
-
132
d
into a desired configuration.
The major benefit provided by EEPROM array
120
is the ability to change the functionality of CPLD
100
(and therefore electronic system
190
) by reprogramming EEPROM array
120
with new configuration data.
FIG. 2
a
shows a conventional process for this reconfiguration operation as applied to system
190
shown in FIG.
1
. In step
210
, power is provided to system
190
, and in step
220
, a set of configuration data (configuration data CFG_DAT shown in
FIG. 1
) is programmed into EEPROM array
120
. Once the programmed data has been verified, system
190
can begin operating with CPLD
100
in a first configuration (configuration A), as indicated in step
230
.
To reconfigure CPLD
100
, the outputs of CPLD
100
are tri-stated, which halts operation of system
190
, as shown in step
240
. EEPROM
120
is then reprogrammed and verified with a new set of configuration data in step
250
. System
190
is restarted in step
260
, resuming operation with CPLD
100
in a new configuration (configuration B) in step
270
. Thus, EEPROM
120
allows CPLD
100
to be reconfigured without making any hardware modifications. CPLD
100
therefore can be designated an in-system programmable (ISP) device.
This ISP capability of CPLD
100
provides substantial operational flexibility to electronic system
190
. Unfortunately, the conventional reconfiguration process shown in
FIG. 2
a
requires that operation of system
190
be halted (step
240
) while EEPROM array
120
is reprogrammed with the new configuration data (step
250
). This interruption of system operation is necessitated by the long programming time associated with EEPROM array
120
. For a modern EEPROM array in a CPLD, the programming time is roughly equal to 10 ms multiplied by the number of row addresses in the EEPROM array, which can result in programming times of several seconds. The programming interval will only increase as the complexity of the interconnect array and the number of macrocells in the CPLD increase. The overall system downtime during reconfiguration also includes overhead associated with preparing for the EEPROM programming operation and also restarting system operation.
FIG. 2
b
shows a timing diagram for the initial configuration and subsequent reconfiguration operations described with respect to
FIG. 2
a
, and shows traces for system power (Vdd), operation of system
190
, and programming of EEPROM array
120
. As shown in
FIG. 2
b
, when system power is first applied at time T
0
, EEPROM programming commences. Once the programming of EEPROM array
120
is completed at time T
1
, system
190
can begin operating with CPLD
100
in a first configuration (configuration A). To place CPLD
100
in a different configuration, operation of system
190
is halted at time T
2
, and reprogramming of EEPROM
120
is performed. At time T
3
, this reprogramming is completed and system
190
can resume operation, this time with CPLD
100
in a second configuration (configuration B). As indicated in
FIG. 2
b
, the time period between times T
0
and T
1
correspond to the “CPLD Configuration at Power-Up” portion of the flow chart shown in
FIG. 2
a
(steps
210
and
220
). Similarly, the time period between times T
1
and T
2
correspond to step
230
, while the time period between times T
2
and T
3
correspond to steps
240
,
250
, and
260
(“CPLD Reconfiguration”). Finally, the portion of the timing diagram after time T
3
corresponds to step
270
.
As noted previously, the downtime system
190
experiences during the reconfiguration operation from time T
2
to time T
3
is necessary to allow CPLD
100
to be reconfigured. In a conventional CPLD that follows the IEEE 1532 standard for ISP use, the only way to reconfigure the system is to apply an ISC_ENABLE instruction that halts the system (by tri-stating the CPLD outputs) to allow the new configuration data to be loaded into the EEPROM array. While this type of operational interruption may be acceptable in certain situations, in general it is much more desirable to minimize or eliminate any system downtime.
Accordingly, it is desirable to provide a system and method for reconfiguring a CPLD without interrupting system operation.
SUMMARY
The invention provides a system and method for rapidly reconfiguring a CPLD. Some modern CPLD architectures, such as those used in the CoolRunner family of CPLDs from Xilinx, Inc., incorporate both an EEPROM array and an SRAM array. A set of configuration data is programmed into the EEPROM, which provides non-volatile storage of that configuration data set. During operation of the CPLD, the configuration data set stored in the EEPROM is transferred into the SRAM array, which controls the configuration of the logic elements of the CPLD. The EEPROM array can then be turned off to minimize device power consumption. The SRAM array in this type of CPLD architecture is sometimes referred to as a “shadow” SRAM array since it reproduces the configuration data set stored in the EEPROM array. The invention uses the EEPROM and SRAM arrays in this type of CPLD to advantageously allow the configuration of a CPLD to be changed so quickly that normal system operation (i.e., operation of the system to perform its intended function) need not be terminated to allow for CPLD reconfiguration.
According to an embodiment of the invention, a method for reconfiguring a CPLD having a shadow SRAM array comprises programming a first set of configuration data into the EEPROM array and transferring that configuration to the SRAM array to place the CPLD in a first configuration. While operating the system with the CPLD in that first configuration, a second set of configuration data can be programmed into the EEPROM array. Because the SRAM array controls the actual configuration of the CPLD, this reprogramming of the EEPROM array does not affect system operation. Then, at a desired point in time, the second set of configuration data in the EEPROM array can be transferred to the SRAM array to place the CPLD in a second configuration. Because write operations to the SRAM array do not involve the time-consuming Fowler-Nordheim tunneling technique used in EEPROM array programming, this data transfer operation can be performed extremely rapidly. For example, while a reprogramming operation for a modern EEPROM array can take roughly 2-3 seconds, programming a similarly sized SRAM array can require less than 20 microseconds. Therefore, in contrast with conventional methods, the reconfiguration process of the invention does not require that normal system operation be t
Darling Roy D.
Davies, Jr. Thomas J.
Shimanek Schuyler E.
Cartier Lois D.
Chan H. C.
Kubodera John
Tan Vibol
Xilinx , Inc.
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