Programming circuitry for configurable FPGA I/O

Details Programming circuitry for configurable FPGA I/O Programming circuitry for configurable FPGA I/O

2000-12-21

2004-01-13

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C326S038000

Reexamination Certificate

active

06678848

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to FPGA technology. More specifically, the present invention relates to programming the configuration of FPGA I/O.
2. The Prior Art
FPGA devices are known in the art. FPGA devices have I/O blocks or cells, logic blocks, and connecting circuitry. Each of these three elements are design elements and may be configured, to various extents, by users. The FPGA I/O cells are configurable, having a selection of I/O features such as LVTTL, 3.3V PCI, 5V PCI, 5V CMOS, GTL, HSTL, etc.
Fuse devices are well known in the art, being used for devices having a relatively small number of gate equivalents. Antifuse devices are a newer technology being used for one-time programmable devices, and have become the implementation choice for devices needing a relatively large number of gate equivalents. Antifuse devices comprise a pair of conductive electrodes separated by at least one layer of antifuse material and may include one or more diffusion barrier layers. Prior to programming, antifuses exhibit very high resistance between the two electrodes and may be considered to be open circuits. A programming process disrupts the antifuse material and creates a low-impedance connection between the two conductive electrodes.
One-time programmable FPGAs may be implemented using any programmable (configurable) media, such as fuse or antifuse substrates. The predominant base technology today is antifuse.
One-time programmable FPGAs also require that I/O be configurable. Current FPGA devices have circuitry dedicated to this I/O configuration task, which necessitates a design and implementation effort solely for that purpose. This adds all the associated monetary costs as well. In addition to the monetary costs, the I/O configuration circuitry uses very valuable real estate (physical layout space) where such space is at a premium. As a final drawback, much, of the I/O configuration circuitry used to permanently set I/O options and configurations for a particular application is not used again. Although the functionality provided by the I/O configuration circuitry is required, much of the circuitry used to provide that functionality in current designs is used very little after initial configuration. Those portions of the circuit not used after configuration therefore waste space and cost.
The inherent costs, layout space usage, and unused circuitry after configuration in current I/O configuration circuitry designs have left an unfilled need to reduce the costs with respect to any of the three aspects. A reduction in any one of the three would result in significant savings and increased reliability over the build quantities found in typical FPGA chips; a reduction in all three areas would be a significant step forward in the area of I/O configuration circuit design.
It is therefore a goal of this invention to provide a method and system for reducing the inherent costs, layout space usage, and the amount of circuitry that remains unused after I/O configuration has taken place in FPGAs.
BRIEF DESCRIPTION OF THE INVENTION
The present invention uses boundary scan registers, a set of components on FPGAs needed to test the FPGAs connectivity once installed on a board, to both address and program a set of individually programmable elements that are then used to determine I/O configurations. The boundary scan registers may be used to do this because they are not normally used for testing until after the FPGA has been programmed—there will be no interference between the two functional uses of the registers. A way has been found to use the boundary scan registers to program configurable I/O, and then, after the I/O is configured, to use the boundary scan registers as they were originally intended: for testing purposes once the FPGA is installed on a board.
According to another aspect of the present invention, the boundary scan registers can also be used to test the FPGA connectivity before programming by simulating the programming and testing the FPGA.
The circuitry needed to use the boundary scan registers in this new and unusual way is substantially less than that used in the prior art to program configurable I/O. There are, overall, fewer registers and fewer individual design elements, which all together use less space on the chip than previous designs. This means that not just one, but all three improvements over the prior art have been reached: the present invention provides a method and system for reducing the inherent costs, layout space usage, and the amount of circuitry that remains unused after I/O configuration has taken place in FPGAs.
The present invention discloses circuitry that interfaces with boundary scan registers, using the contents of the boundary scan registers to first address individually programmable elements and then to program those same elements. The individually programmed elements are configured to permanently enable or disable (as requirements dictate) configurable I/O features. Finally, there is provided a new individual program element test circuit, which will read 0 if the individual element has not been programmed, or a 1 if it has been programmed (regardless of the value of the programming). This allows the individual programmable elements of each I/O cells to be checked to see if they have been programmed or not, providing a way to establish the status or success/failure of previous programming.


REFERENCES:
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 5991908 (1999-11-01), Baxter et al.
patent: 6242943 (2001-06-01), El-Ayat
patent: 6392437 (2002-05-01), El-Ayat
patent: 2003/0020512 (2003-01-01), Mantey et al.
Luis Morales, The Programmable Logic Data Book, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, published 1994, pp. 8-45 to 8-50.*
Using JTAG Boundary-Scan with ProASIC™ 500K Devices, available from Actel Corporation, 955 East Arques Avenue, Sunnyvale, California 94086, published Nov. 2000, pp. 1-10.

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