Programming and verification address generation for random acces

Details Programming and verification address generation for random acces Programming and verification address generation for random acces

1998-06-11

2000-10-03

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

711219, 365236, 326 39, G06F 1202

Patent

active

061286923

ABSTRACT:
A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.

REFERENCES:
patent: Re34444 (1993-11-01), Kaplinsky
patent: 4642487 (1987-02-01), Carter
patent: 4670749 (1987-06-01), Freeman
patent: 4706216 (1987-11-01), Carter
patent: 4758985 (1988-07-01), Carter
patent: 4791603 (1988-12-01), Henry
patent: 4870302 (1989-09-01), Freeman
patent: 5089993 (1992-02-01), Neal et al.
patent: 5128559 (1992-07-01), Steele
patent: 5237219 (1993-08-01), Cliff
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5432719 (1995-07-01), Freeman et al.
patent: 5469003 (1995-11-01), Kean
patent: 5469400 (1995-11-01), Yamano
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5572148 (1996-11-01), Lytle et al.
patent: 5778439 (1998-07-01), Trimberger et al.
patent: 5781756 (1998-07-01), Hung
patent: 5821773 (1998-10-01), Norman et al.
William I. Fletcher et al., "Simplify Sequential Circuit Designs", Electronic Design, Jul. 8, 1971, pp. 70-72.
Albert Hemel, "Making Small ROM's [sic] Do Math Quickly, Cheaply and Easily", Electronics, May 11, 1970, pp. 104-111.
S.C. Hu, "Cellular Synthesis of Synchronous Sequential Machines", IEEE Trasactions on Computers, Dec. 1972, pp. 1399-1405.
Yahiko Kambayashi, "Logic Design of Programmable Logic Arrays", IEEE Transactions on Computers, vol. C-28, No. 9, Sep. 1979, pp. 609-617.
Floyd Kvamme, "Standard Read-Only Memories Simplify Complex Logic Design", Electronics, Jan. 5, 1970, pp. 88-95.
John L. Nichols, "A Logical Next Step for Read-Only Memories", Electronics, Jun. 12, 1967, pp. 111-113.
"Optimized Reconfigurable Cell Array (ORCA) Series Field-Programmable Gate Arrays," Advanced Data Sheet, Feb. 1993, AT&T Microelectronics, pp. 1-87.
E.W. Page, "Programmable Array Realizations of Sequential Machines," Department of Electrical Engineering, Duke University, Doctoral Dissertation, 1973.
Howard A. Sholl et al., "Design of Asynchronous Sequential Networks Using Read-Only Memories", IEEE Transactions on Computers, vol. C-24, No. 2, Feb. 1975, pp. 195-206.
The Programmable Logic Data Book, Xilinx, Inc., 1994, pp. 2-5 through 2-102.
Arnold Weinberger, "High-Speed Programmable Logic Array Adders", IBM J. Res. Develop., vol. 23, No. 2, Mar. 1979, pp. 163-178.

Affiliated with

Also associated with

Rating

Programming and verification address generation for random acces does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programming and verification address generation for random acces, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programming and verification address generation for random acces will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-205430