Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-02-27
2007-02-27
Huynh, Andy (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S594000
Reexamination Certificate
active
10944244
ABSTRACT:
A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.
REFERENCES:
patent: 4288256 (1981-09-01), Ning et al.
patent: 5413949 (1995-05-01), Hong
patent: 5741719 (1998-04-01), Kim
patent: 5923976 (1999-07-01), Kim
patent: 6153472 (2000-11-01), Ding et al.
patent: 6297097 (2001-10-01), Jeong
patent: 6300196 (2001-10-01), Chang
patent: 6342715 (2002-01-01), Shimizu et al.
patent: 6495467 (2002-12-01), Shin et al.
patent: 6602750 (2003-08-01), Kao
patent: 6627942 (2003-09-01), Wang
patent: 6806132 (2004-10-01), Mori et al.
patent: 6897116 (2005-05-01), Lee et al.
patent: 6908817 (2005-06-01), Yuan
patent: 6943118 (2005-09-01), Chen et al.
patent: 2004/0057264 (2004-03-01), Houdt
Kitamura, “A Low Voltage Operating Flash Memory Cell with High Coupling Ratio Using Homed Floating Gate with Fine HSG,” IEEE 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 104-105.
Chindalore Gowrishankar L.
Swift Craig T.
Chiu Joanna G.
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Goodwin David
Huynh Andy
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