Programming and erasing structure for a floating gate memory...

Details Programming and erasing structure for a floating gate memory... Programming and erasing structure for a floating gate memory...

2006-08-22

2006-08-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000

Reexamination Certificate

active

07094645

ABSTRACT:
A floating gate memory cell has a floating gate in which there are two adjacent floating gate layers. The top layer is made to have a contour while leaving the lower layer substantially unchanged. An interlevel dielectric and a control gate follow the contour of the floating gate to increase capacitance between the control gate and the floating gate. The two layers of the floating gate can be polysilicon in which the top layer has the contour formed therein by use of a sacrificial layer. The sacrificial layer is formed over the bottom polysilicon layer and etched. The top polysilicon layer is formed over the sacrificial layer. Subsequent processing of the top polysilicon layer exposes the remaining portion of the sacrificial layer so it can be removed; leaving the contour in the top polysilicon layer for the interlevel dielectric and the control gate.

REFERENCES:
patent: 4288256 (1981-09-01), Ning et al.
patent: 5923976 (1999-07-01), Kim
patent: 6391722 (2002-05-01), Koh
patent: 6537880 (2003-03-01), Tseng
patent: 6627942 (2003-09-01), Wang
patent: 6716705 (2004-04-01), Mehta et al.
patent: 6780712 (2004-08-01), Hsieh
patent: 6791142 (2004-09-01), Tseng
patent: 6867098 (2005-03-01), Park et al.
patent: 6908817 (2005-06-01), Yuan
patent: 2004/0057264 (2004-03-01), Houdt
patent: 2004/0229422 (2004-11-01), Mori et al.

Affiliated with

Also associated with

Rating

Programming and erasing structure for a floating gate memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programming and erasing structure for a floating gate memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programming and erasing structure for a floating gate memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3658884