Programmable weak write test mode

Details Programmable weak write test mode Programmable weak write test mode

2002-05-08

2004-08-17

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S154000, C365S185220, C365S189090, C365S190000, C365S230060

Reexamination Certificate

active

06778450

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit memory devices. In particular, the present invention relates to circuits for testing memory cells.
2. Background Information
A prior art static random access memory (SRAM) commonly includes an array of SRAM cells. Each SRAM cell is capable of storing data using a pair of cross-coupled devices, such as inverters. Pull-up gates in the cross-coupled devices usually prevent leakage currents in a SRAM cell from discharging the internal data storage nodes of the SRAM cell.
Defects sometimes occur during the manufacturing process that can impair the functionality of the SRAM cells. A symmetric defect impairs the performance of both cross-coupled devices of the SRAM cell equally. On the other hand, an asymmetric defect normally impairs only one of the cross-coupled devices. A defective pull-up in one inverter is an example of an asymmetric defect.
Manufacturing quality testing procedures are provided to detect such defects in newly manufactured integrated circuits. One test described in U.S. Pat. No. 5,559,745, considered to Banik et al is a “weak write” test, which uses on-die test circuitry to stress each SRAM cell with a pre-designed “weak write” stress that will pass a good cell and fail a cell with significant device or interconnect defects. In this test, data (e.g., a logic level “1”) is written to a memory cell, a complement of the data (e.g., a logic level “0”) is then weakly written to the memory cell, and the memory cell is then read to determine whether the weak write of the data complement overwrote data written to the memory cell. If the weak write of the data complement overwrote the data written to the memory cell, then the memory cell is deemed defective. If the weak write of the data complement did not overwrite the data written to the memory cell, then a weak write test is repeated on the memory cell using opposite logic levels. For example, opposite data (e.g., a logic level “0”) is written to the memory cell, the opposite data complement (e.g., a logic level “1”) is then weakly written to the memory cell, and the memory cell is then read to determine whether the weak write of the opposite data complement overwrote the opposite data written to the memory cell. If the weak write of the opposite data complement did overwrite the opposite data written to the memory cell, then the memory cell is deemed defective, and the test may be terminated. Common defects failing weak-write stresses can include missing salicide junctions, internal metal shorts, source/drain dislocations, and light p-tip dose.
The current weak write circuitry is limited, however, because the pre-designed stress point does not adequately track manufacturing process variations and/or manufacturing process modifications. For example, this means that tests using the current weak write circuitry may fail memory cells that should be passed or vice versa because of process variations and/or modifications, which may cause undesirably lower test yields or under-tested parts. Furthermore, the current weak write circuitry cannot evaluate manufacturing process variations/modifications and their effects on the appropriateness of the stress point used to determine whether or not a memory cell is defective.
Even if the prior art weak write circuitry could track and evaluate manufacturing process variations and/or modifications and the evaluation indicated that the stress point needed to be changed, the prior art weak write circuitry cannot change the stress point post-silicon except through use of a small number of environmental factors. This is because each weak write circuit has only one stress point set by pre-silicon design factors. This is troublesome because many pre-silicon and post-silicon factors affect the optimization of the choice of stress point.


REFERENCES:
patent: 5559745 (1996-09-01), Banik et al.
patent: 5835429 (1998-11-01), Schwarz
patent: 6192001 (2001-02-01), Weiss et al.
patent: 6256241 (2001-07-01), Mehalel
patent: 6501692 (2002-12-01), Melanson et al.
patent: 6552941 (2003-04-01), Wong et al.

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