Programmable universal test interface for testing memories with

Details Programmable universal test interface for testing memories with Programmable universal test interface for testing memories with

1998-06-18

2000-03-28

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714725, 714726, 714733, H04B 1700

Patent

active

060444819

ABSTRACT:
A programmable memory test interface for testing a memory device is disclosed. The interface includes a plurality of programmable input pins and output pins. The interface also includes a logic interfacing means for connecting external signals to the plurality of programmable input pins and output pins. The external signals are processed by the logic interfacing means and then communicated to a plurality of memory connection pins that couple up to the memory device. The logic component means is capable of being configured in accordance with one or more memory testing methodologies including a serial built-in-self-test (BIST), a parallel built-in-self-test (BIST), a parallel test, a serial test, and a scan test. The configuring is performed by selectively interconnecting selected ones of the plurality of input pins and output pins to the external signals that drive the logic interface means in a test mode that operates in one or more memory testing methodologies or a mission mode.

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