Programmable universal test interface and method for making the

Details Programmable universal test interface and method for making the Programmable universal test interface and method for making the

1997-05-09

1999-10-19

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714725, 714733, H04B 1700

Patent

active

059681926

ABSTRACT:
Disclosed is a programmable memory test interface. The test interface includes logic circuitry configured to be integrated to a memory device. The memory device has a plurality of receiving connections that are configured to be coupled to a plurality of internal connections that couple to the logic circuitry. The interface further includes a plurality of programmable input pins and output pins leading to and from the logic circuitry, and the programmable input pins and output pins are configured to receive control signals from a test controller for operating the memory device in either a test mode or a mission mode. The programmable input pins and output pins are selectively interconnected to transform the logic circuitry into at least one type of memory testing methodology interface.

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