Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-08-08
2006-08-08
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
07089470
ABSTRACT:
Programmable test pattern driver and capture mechanisms for boundary scan cluster or functional block testing. A boundary scan test system includes at least one device under test. The device may include a Test Access Port (TAP) controller, a plurality of output AC boundary scan cells (BSCs), and a plurality of input AC BSCs. The device may further include a programmable AC_Pattern_Source signal generator configured to produce AC signal patterns that selectively remain unchanged for at least one cycle before and after an original capture cycle location, a programmable AC_Sync signal generator configured to independently control the AC_Sync signal to lead or lag an original cycle location at full cycle increments, a programmable phase controller configured to independently control either the rising or falling edge aligned AC_Pattern_Clock signal or AC_Counter_Clock signal, and an AC_Test_Clock signal switcher configured to selectively utilize one of a plurality of clock signals including a TCK signal.
REFERENCES:
patent: 6122762 (2000-09-01), Kim
patent: 6430718 (2002-08-01), Nayak
patent: 6807644 (2004-10-01), Reis et al.
Baeg Sang Hyeon
Chung Sung Soo
Jun Hong-shin
Cisco Technology Inc.
Robbins Steven J.
Thelen Reid & Priest LLP
Tu Christine T.
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