Programmable state machine of an integrated circuit

Details Programmable state machine of an integrated circuit Programmable state machine of an integrated circuit

2002-09-30

2008-12-09

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07464310

ABSTRACT:
A programmable state machine of an application specific integrated circuit (ASIC) is programmed by enabling the scan mode of the integrated circuit. The process of programming the state machine continues by loading, through at least one scan chain to which the state machine is coupled, at least one timing sequence instruction into scan capable registers of the state machine. Once the at least one timing sequence instruction has been loaded into the scan capable registers, the scan mode is disabled and normal mode of the integrated circuit is resumed.

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Himanshu Bhatnagar, Kluwer Academic Publishers, “Advanced ASIC Chip Synthesis” Second Edition, Copyright 2002.

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