Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2005-10-25
2005-10-25
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S205000, C365S233100
Reexamination Certificate
active
06958943
ABSTRACT:
A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.
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“Fast Dram Sensing with Sense Amplifiers Synchronous to Bitline Delays,”IBM Technical Disclosure Bulletin,Mar. 1987, pp. 4637-4639, vol. 29, No. 10.
Chan Yuen H.
Charest Timothy J.
Rawlins John R.
Tuminaro Arthur D.
Wadhwa Jatinder K.
Augspurger Lynn L.
Dinh Son T.
International Business Machines - Corporation
Marhoefer Laurence J.
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