Programmable semiconductor memory device

Details Programmable semiconductor memory device Programmable semiconductor memory device

1999-12-01

2001-07-17

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S230030, C365S230010, 37, 37, 37

Reexamination Certificate

active

06262924

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor memory devices, and more particularly to a programmable semiconductor memory device such as a mask read only memory (ROM) which can be programmed by a mask which is used during the chip production process in order to record data.
SUMMARY OF THE INVENTION
First, a description will be given of a first conceivable example of the mask ROM, by referring to
FIGS. 1 through 4
.
FIG. 1
shows an important part of the first conceivable example of the mask ROM. In
FIG. 1
, an address buffer
1
is used to input to the inside an address signal AIN which is supplied from the outside. The address signal AIN is input to an address signal input terminal
2
. An internal chip enable signal CEB is input to an internal chip enable signal input terminal
3
. This internal chip enable signal CEB has the same phase relationship to a chip enable signal /CE which is supplied from the outside and specifies whether to put an internal circuit to an active state or to an inactive or standby state. In this specification, the symbol “/” in front of a signal name such as /CE indicates an inverted signal of CE (or “CE bar”). The address buffer
1
includes an OR circuit
4
, and an internal address signal ADD which has the same phase relationship to the address signal AIN which is supplied from the outside is output from an internal address signal output terminal
5
.
An address pulse signal generating circuit
6
generates an address pulse signal ADDP (address transition signal ATD) which indicate a transition of the address signal AIN when the address signal AIN makes the transition. The address pulse signal generating circuit
6
includes inverters
7
through
9
, OR circuits
10
through
12
, and an AND circuit
13
.
An output control pulse signal generating circuit
14
generates an output control pulse signal ALP for controlling output of data read from a memory cell array (not shown) to the outside. A chip enable pulse signal CEP which is generated when the chip enable signal /CE makes a transition from a high potential (high level) to a low potential (low level) is input to a chip enable pulse signal input terminal
15
. The output control pulse signal generating circuit
14
includes an OR circuit
16
, and the output control pulse signal ALP is output from an output control pulse signal output terminal
17
.
FIG. 2
shows a CEB and CEP signal generating circuit which generates the internal chip enable signal CEB and the chip enable pulse signal CEP.
The CEB and CEP signal generating circuit shown in
FIG. 2
includes a chip enable signal input terminal
18
to which the chip enable signal /CE is input, inverters
19
through
22
, an OR circuit
23
, an AND circuit
24
, an internal chip enable signal output terminal
25
from which the internal chip enable signal CEB is output, and a chip enable pulse signal output terminal
26
from which the chip enable pulse signal CEP is output.
FIG. 3
is a timing chart for explaining the operation of the CEB and CEP signal generating circuit shown in FIG.
2
. In
FIG. 3
, (A) shows the voltage waveform of the chip enable signal /CE, (B) shows the voltage waveform of the internal chip enable signal CEB, and (C) shows the voltage waveform of a chip enable pulse signal CEP.
Accordingly, the waveforms at various parts of the circuit shown in
FIG. 1
become as shown in FIG.
4
. In
FIG. 4
, (A) shows the voltage waveform of the address signal AIN, (B) shows the voltage waveform of the chip enable signal /CE, and (C) shows the voltage waveform of the internal chip enable signal CEB. In addition, in
FIG. 4
, (D) shows the output voltage waveform of the OR circuit
10
, (E) shows the output voltage waveform of the OR circuit
11
, and (F) shows the voltage waveform of the address pulse signal ADDP. Further, in
FIG. 4
, (G) shows the voltage waveform of the chip enable pulse signal CEP, (H) shows the voltage waveform of the output control pulse signal ALP, and (I) shows the transition of the output data DOUT.
In other words, according to the first conceivable example of the mask ROM, the output data DOUT is output in synchronism with the falling edge of the output control pulse signal ALP.
In
FIG. 4
, t
CE
shown in (I) indicates a chip enable access time from a time when the address is ascertained by the transition of the chip enable signal /CE from the high level (inactive level) to the low level (active level) to a time when the output data DOUT is output.
Next, a description will be given of a second conceivable example of the mask ROM, by referring to
FIGS. 5 and 6
.
FIG. 5
shows an important part of the second conceivable example of the mask ROM. In
FIG. 5
, an address buffer
27
is used to input to the inside an address signal AIN which is supplied from the outside. The address signal AIN is input to an address signal input terminal
28
. A chip enable signal /CE is supplied from the outside to a chip enable signal input terminal
29
.
The address buffer
27
includes a chip enable signal input terminal
30
which is input with an internal chip enable signal CE which has an inverted relationship to the chip enable signal /CE, a NOR circuit
31
, inverters
32
through
37
, and NAND circuits
38
and
39
. The address buffer
27
also includes an internal address signal output terminal
40
from which an internal address signal ADD is output, and an internal address signal output terminal
41
from which an internal address signal /ADD is output. The internal address signal ADD has the same phase relationship to the address signal AIN, and the internal address signal /ADD has the inverted relationship to the internal address signal ADD.
An address pulse signal generating circuit
42
generates an address pulse signal ADDP. The address pulse signal generating circuit
42
includes NOR circuits
43
and
44
, inverters
45
through
51
, a NAND circuit
52
, and an OR circuit
53
.
An output control pulse signal generating circuit
54
includes a chip enable pulse signal input terminal
55
to which a chip enable pulse signal CEP is input, an OR circuit
56
, and an output pulse signal output terminal
57
from which an output control pulse signal ALP is output.
FIG. 6
is a timing chart for explaining the operation of the circuit shown in FIG.
5
.
In
FIG. 6
, (A) shows the voltage waveform of the address signal AIN, (B) shows the voltage waveform of the chip enable signal /CE, and (C) shows the voltage waveform of the internal chip enable signal CE. In addition, in
FIG. 6
, (D) shows the voltage waveform of the address pulse signal ADDP, (E) shows the voltage waveform of the chip enable pulse signal CEP, (F) shows the voltage waveform of the output control pulse signal ALP, and (G) shows the transition of the output data DOUT.
In this second conceivable example of the mask ROM, the output data DOUT is also output in synchronism with the falling edge of the output control pulse signal ALP.
In
FIG. 6
, t
CE
shown in (G) indicates a chip enable access time from a time when the address is ascertained by the transition of the chip enable signal /CE from the high level (inactive level) to the low level (active level) to a time when the output data DOUT is output.
Next, a description will be given of a third conceivable example of the mask ROM, by referring to
FIGS. 7 through 10
.
FIG. 7
shows an important part of the third conceivable example of the mask ROM. In
FIG. 7
, a chip body
58
includes memory cell arrays
59
through
62
having a 1024×1024×2 bit construction, an address buffer
63
, row decoders
64
and
65
, column decoders
66
through
69
, sense amplifiers
70
through
73
, an output buffer
74
, and a logic circuit
75
.
Row address signals A
0
through A
9
and column address signals A
10
through A
19
are input to the address buffer
63
. The row decoder
64
decodes the row address signals A
0
through A
9
output from the address buffer
63
, and selects a block selection line and a word line with respect to the memory cell

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