Programmable MOS device formed by stressing polycrystalline...

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S100000, C365S189110, C365S225700

Reexamination Certificate

active

07079412

ABSTRACT:
A programmable memory circuit and a method for programming the same are disclosed. A polycrystalline silicon resistor pair are used in a programmable memory cell. The pair includes a first polycrystalline silicon resistor stressable by a predetermined current thereacross, and a second polycrystalline silicon resistor similarly structured as the first polycrystalline silicon resistor stressable by the predetermined current, wherein when only the first resistor is stressed by the predetermined current, a resistance of the first resistor is lowered as compared to the unstressed second resistor, thereby programming the memory cell.

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patent: 6507087 (2003-01-01), Yu
Ker, Ming-Dou et al., “Capacitor-Couple ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS ASIC”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, No. 3, (Sep. 1996), pp. 307-321.
Ker, Ming-Dou et al., “Complementary-SCR ESD Protection Circuit with Interdigitated Finger-Type Layout for Input Pads of Submicron CMOS IC's”, IEEE Transactions on Electron Devices, vol. 42, No. 7, (Jul. 1995), pp. 1297-1304.
Wu et al., A New On-Chip ESD Protection Circuit with Dual Parasitic SCR Structures for CMOS VLSI, IEEE Journal of Solid-State Circuits, vol. 27, No. 3, (Mar. 1992), pp. 274-280.

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