Programmable logic devices

Details Programmable logic devices Programmable logic devices

2004-12-06

2009-10-20

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S114000, C326S039000

Reexamination Certificate

active

07606969

ABSTRACT:
An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.

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patent: 6429682 (2002-08-01), Schultz et al.
patent: 2004/0193798 (2004-09-01), Kuwamura
“FPGA-based Fine Grain Processor Array Design Considerations”, Proceedings of the Third IEEE International Conference on Electronics, Circuits, and Systems, vol. 2, Oct. 13-16, 1996, pp. 659-662.

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