Sensing with bit-line lockout control in non-volatile memory

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185220, C365S185030, C365S185170, C365S185250, C365S227000, C365S185020

Reexamination Certificate

active

07492640

ABSTRACT:
In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.

REFERENCES:
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5595924 (1997-01-01), Yuan et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5768192 (1998-06-01), Eitan
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6657891 (2003-12-01), Shibata et al.
patent: 7170784 (2007-01-01), Cernea et al.
patent: 7173854 (2007-02-01), Cernea et al.
patent: 7196931 (2007-03-01), Cernea et al.
patent: 7251160 (2007-07-01), Li et al.
patent: 2004/0057287 (2004-03-01), Cernea et al.
patent: 2005/0057967 (2005-03-01), Khalid et al.
patent: 2005/0078524 (2005-04-01), Hosono
patent: 2005/0169082 (2005-08-01), Cernea et al.
patent: 2006/0209592 (2006-09-01), Li et al.
patent: 2006/0221693 (2006-10-01), Cernea et al.
Eitan et al., “NROM: A Novel Localized Trapping 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” corresponding International Patent Application No. PCT/US2008/065681, mailed on Oct. 2, 2008, 15 pages.
USPTO, “Notice of Allowance and Fee(s) Due,” mailed in related U.S. Appl. No. 11/759,909 on Oct. 8, 2008, 17 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Sensing with bit-line lockout control in non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sensing with bit-line lockout control in non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sensing with bit-line lockout control in non-volatile memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4112373

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.