Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-05-23
2011-12-27
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S726000, C714S727000, C714S729000, C326S038000, C326S039000, C326S041000
Reexamination Certificate
active
08086922
ABSTRACT:
Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a programmable logic device integrated circuit by receiving configuration data with the differential communications circuitry and storing the received configuration data in nonvolatile memory. The nonvolatile memory may be located in an external integrated circuit such as a configuration device or may be part of the programmable logic device integrated circuit. The stored configuration data may be loaded into configuration memory in the programmable logic device to program the device to perform a desired custom logic function. The differential communications circuitry may be used to handle boundary scan tests and programmable scan chain tests. During user mode operations the differential communications circuitry carries user data traffic.
REFERENCES:
patent: 5748559 (1998-05-01), Raza et al.
patent: 6243842 (2001-06-01), Slezak et al.
patent: 6553523 (2003-04-01), Lindhom et al.
patent: 6650140 (2003-11-01), Lee et al.
patent: 6766406 (2004-07-01), Gasperini et al.
patent: 6831480 (2004-12-01), Shumarayev et al.
patent: 6937493 (2005-08-01), Krause et al.
patent: 6983441 (2006-01-01), Wescott
patent: 7080789 (2006-07-01), Leaming
patent: 7181649 (2007-02-01), Fruhauf et al.
patent: 7210081 (2007-04-01), Euzent et al.
patent: 7298646 (2007-11-01), Turner
patent: 7302562 (2007-11-01), Jacobson et al.
patent: 7313730 (2007-12-01), Ryser
patent: 7363545 (2008-04-01), Jacobson et al.
patent: 7373522 (2008-05-01), Leaming
patent: 7454556 (2008-11-01), Knapp
patent: 7669037 (2010-02-01), Schumacher et al.
patent: 7795909 (2010-09-01), Daxer et al.
patent: 2003/0115523 (2003-06-01), Lavie et al.
patent: 2004/0078716 (2004-04-01), Schulze et al.
patent: 2008/0195154 (2008-08-01), Brown et al.
“FTDI Chip—FT245BM USB FIFO (USB—Parallel) I.C.; DS245B Version 1.4” Data Sheet of Future Technology Devices Intl. Ltd (2004) pp. 1-24.
“GL603USB; GL603USB-A; GL603USB-B; USB + PS/2 Mouse Microcontroller; Specification 1.4” Data Sheet of Genesys Logic, Inc., Sep. 22, 2000; pp. 1-41.
“GL800USB USB2.0 UTMI Compliant Transceiver; Specification 1.2” Aug. 20, 2002 Data Sheet of Genesys Logic, Inc., pp. 1-24.
“MasterBlaster Serial/USB Communications Cable User Guide”; User Guide of Altera Corporation, Jul. 2004, pp. i-viii; pp. 1-1 to 1-6, and pp. 2-1 to 2-8.
“USB-Blaster Download Cable User Guide”; User Guide of Altera Corporation, Dec. 2004, pp. i-iv; pp. 1-1 to 1-6, and pp. 2-1 to 2-8.
Siripokarpirom, “A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test”, 2005, IEEE, pp. 505-508.
Altera Corporation
Kellogg David C.
Tabone, Jr. John J
Treyz G. Victor
Treyz Law Group
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