Programmable logic device providing a serial peripheral...

Details Programmable logic device providing a serial peripheral... Programmable logic device providing a serial peripheral...

2006-06-02

2008-05-27

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S040000

Reexamination Certificate

active

07378873

ABSTRACT:
Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). For example, in accordance with one embodiment of the present invention, a PLD includes volatile memory adapted to store configuration data to configure the PLD for its intended function. The PLD further includes non-volatile memory adapted to store configuration data which is transferable to the volatile memory to configure the PLD for its intended function. The PLD further includes a serial peripheral interface (SPI) port adapted to receive configuration data from an external device for transfer into one of the volatile memory and the non-volatile memory.

REFERENCES:
patent: 5548228 (1996-08-01), Madurawe
patent: 5640107 (1997-06-01), Kruse
patent: 5689516 (1997-11-01), Mack et al.
patent: 5696455 (1997-12-01), Madurawe
patent: 5794033 (1998-08-01), Aldebert
patent: 6038185 (2000-03-01), Ng
patent: 6044025 (2000-03-01), Lawman
patent: 6049222 (2000-04-01), Lawman
patent: 6150837 (2000-11-01), Beal et al.
patent: 6304099 (2001-10-01), Tang et al.
patent: 6356107 (2002-03-01), Tang et al.
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6483342 (2002-11-01), Britton et al.
patent: 6507214 (2003-01-01), Snyder
patent: 6538468 (2003-03-01), Moore
patent: 6564285 (2003-05-01), Mills
patent: 6704850 (2004-03-01), Reynolds
patent: 6714041 (2004-03-01), Darling et al.
patent: 6721840 (2004-04-01), Allegrucci
patent: 6732263 (2004-05-01), May et al.
patent: 6772230 (2004-08-01), Chen et al.
patent: 6774668 (2004-08-01), Wirtz, II
patent: 6785165 (2004-08-01), Kawahara
patent: 6828823 (2004-12-01), Tsui et al.
patent: 6851047 (2004-12-01), Tsui et al.
patent: 6873177 (2005-03-01), Wennekamp et al.
patent: 6903574 (2005-06-01), Chen et al.
patent: 7081771 (2006-07-01), Agrawal et al.
patent: 7088132 (2006-08-01), Tang et al.
patent: 7095247 (2006-08-01), Tang et al.
patent: 7190190 (2007-03-01), Camarota et al.
patent: 2004/0061147 (2004-04-01), Fujita
patent: 2004/0064622 (2004-04-01), Smith
patent: 2005/0189962 (2005-09-01), Agrawal et al.
patent: 2006/0119384 (2006-06-01), Camarota et al.
Serial Peripheral Interface Bus—Wikipedia, the free enclyclopedia, Jan. 6, 2007, p. 1-7.
“Low-Cost FPGA Configuration Via Industry-Standard SPI Serial Flash & LatticeECP/EC EPGAs,” White Paper, Jun. 2004, Lattice Semiconductor Corporation.
AT17LV(A) Series FPGA Configuration Memory , Ref. 0437K-CNFG-May 2003, pp. 1-18, ATMEL Corporation.
FPGA Configuration EEPROM Memory, 2322F-CNFG, Jun. 2006, pp. 1-18, ATMEL Corporation.
FPGA Configuration EEPROM Memory, 2321E-CNFG, Jun. 2003, pp. 1-24, ATMEL Corporation.
Lattice Semiconductor Corporation, MachXO Family Data Sheet, Version 02.1, May 2006, pp. 1-93.
Altera® Section III User Flash Memory, Max II Device Handbook, vol. 1, 2005, 80 pages, no month.
Actel ProAsic® 3 Flash Family FPGAs with Optional Soft ARM® Support, Advanced v0.6, Apr. 2006, 208 pages.
Altera Corporation, Cyclone Device Handbook, vol. 1, 13, Configuring Cyclone FPGAs, Aug. 2005, 50 pages.
Lattice Semiconductor Corporation, Low-Cost FPGA Configuration Via Industry-Standard SPI Serial Flash, A Lattice Semiconductor White Paper, Jun. 2004, 13 pages.
Xilinx®, Configuring Spartan-3E Xinlnx FPGAs with SPI Flash Memories, Arthur Khu, Jan. 3, 2006, 16 pages.
ST Microelectronics, M25P80, 8 Mbit, Low Voltage, Serial Flash Memory With 40 MHz SPI Bus Interface, Aug. 2004, 41 pages.
U.S. Appl. No. 11/397,985, Fontana.
U.S. Appl. No. 11/398,437, Tang.
U.S. Appl. No. 11/446,309, Tang.
U.S. Appl. No. 11/293,941, Tang.
U.S. Appl. No. 11/350,436, Tang et al.
U.S. Appl. No. 11/348,817, Chen et al.
Lattice Semiconductor Corporation, ispXP Configuration Usage Guidelines, Technical Notes TN1026, Aug. 2002, pp. 1-18.
Lattice Semiconductor Corporation, ispXPGA™ Family, Data Sheet, Jul. 2005, 115 pages.
Lattice Semiconductor Corporation, ispXPGA™ Family, Preliminary Data Sheet, Dec. 2002, pp. 1-90.
Lattice Semiconductor Corporation, LatticeXP Family Data Sheet, Version 01.0, Feb. 2005, 77 pages.
Altera, MAX II Device Handbook, http://www.altera.com, M115V1-1.7, 330 pages, date N/A.
Xilinx, On the Fly Reconfiguration with CoolRunner-II CPLDs, Application Note: CoolRunner-II CPLDs, May 15, 2003, pp. 1-10.
Actel Corporation, “ProASIO Plus Flash Family FPGAs”, v.5.3 May 2006, 173 pages.
Actel Corporation, ProASIC3 Flash Family FPGAs, ARM7 Soft IP Support in ProASIC3E ARM7-Ready Devices, Oct. 2005, 166 pages.

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