Programmable logic device memory blocks with adjustable timing

Details Programmable logic device memory blocks with adjustable timing Programmable logic device memory blocks with adjustable timing

2008-01-15

2008-01-15

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189080, C365S189120, C365S194000, C365S230050, C365S230060, C365S230080

Reexamination Certificate

active

11357629

ABSTRACT:
Programmable logic device integrated circuits with adjustable register and memory address decoder circuitry are provided. The integrated circuits contain programmable memory blocks and programmable logic that is configured by a user. Depending on the type of user logic that is implemented by the user, the programmable logic device integrated circuit may have different timing needs for its memory blocks. The adjustable register and memory address decoder circuitry has associated programmable elements that are loaded with configuration data. The configuration data adjusts the timing characteristics of the adjustable register and memory address decoder circuitry to accommodate the user logic. The adjustable register and memory address decoder circuitry may be used to make setup and clock-to-output timing adjustments to optimize a logic design.

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