Programmable logic core adapter

Details Programmable logic core adapter Programmable logic core adapter

2002-07-26

2004-06-01

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S039000, C326S040000, C326S041000, C714S724000

Reexamination Certificate

active

06744274

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to programmable logic elements, and in particular, to structures and techniques for allowing programmable logic to be embedded into customized integrated circuits such as Application Specific Integrated Circuits (ASICs) and Systems On a Chip (SOP).
BACKGROUND OF THE INVENTION
Observers of the semiconductor industry cannot help but be impressed by the relentless advance of technology. As manufacturing technologies improve, and provide continuously lower cost, increased density parts, design teams in their intensely competitive markets strive to take advantage of the technology with ever increasingly complex devices. In devices as common as cell phone handsets or camcorders it is becoming typical to see microprocessors, DSPs, and major blocks of functionality all on the same device. About the only technology that is yet to be integrated in these multi-million gate, system-chip developments is reprogrammable logic. This is quickly becoming the next target for system-chip integration.
Embedded programmable logic offers the promise of reducing project schedules by implementing high-risk design blocks so that during chip bringup, designs can be quickly re-programmed and modified without the long, costly process of redesigning new versions of silicon. Embedded programmable logic also enables field upgrades of complex algorithms or of blocks implementing protocols for evolving standards. As process geometries continue to shrink and engineering, mask and prototype silicon costs go up, embedded reprogrammable logic will enable multiple product versions to be built from a single die, leveraging those costs over multiple products.
The integration of reprogrammable logic into system chips, however, faces many technical hurdles and requires novel application of tools and systems. Reprogrammable logic by its very nature must be uniquely handled at each stage of the designing process. The right set of models and data must be available for each step from synthesis, through layout, to full chip timing analysis and simulation. Some of the key requirements for embedded programmable logic include the following: scalable programmable gate capacity and I/O bandwidth with support for implementing multiple programmable blocks on a single chip; silicon-efficient support for both control and datapath functions; in-field reprogrammability; standard CMOS process and design that is easily portable to multiple foundries; synthesizable models of the test and programming interfaces; complete Built-in Self-Test capability and support for integration within overall ASIC test methodology; support for the synthesis, simulation, timing analysis and physical design tools of the leading ASIC EDA vendors; architecture-specific synthesis libraries; accurate timing models and an effective methodology for achieving timing closure within the context of the entire chip; and frame layouts with support for ASIC power and feed-thru routing methodologies.
Co-pending U.S. application Ser. No. 09/475,400 dramatically advances the state of the art of programmable logic by introducing the concept of the “Multi-Scale Array” (MSA). Programmable Logic Cores (PLCs) based on this high-speed configurable logic structure enable the development of a new class of complex cell-based ASICs and configurable SOCs. SOC/ASIC designs incorporating these PLCs offer the best of both FPGA and ASIC worlds by combining the flexibility of FPGAs with the price and performance advantages of cell based ASICs.
It remains desirable for structures and methodologies that enable system chip designers to embed programmable logic cores (PLCS) into an overall design while not introducing additional problems, thus enabling design teams to reduce project risk by placing the high-risk parts of their designs in programmable logic. Particularly where there is a risk of changing standards, such as in communications, field reprogrammability offers the options of accelerating development programs, early release to production and low-cost, low-risk field upgrades of products.
SUMMARY OF THE INVENTION
The present invention relates to programmable logic devices. A programmable logic core (PLC) in accordance with the invention can be integrated into custom ICs such as ASICs and SOCs. An example PLC for integration into a custom IC includes a programmable logic array, an application circuit interface (ACI) that provides signal interface between the programmable logic array and application circuitry, and a PLC adapter that initiates and loads the configuration data for the programmable logic array and interfaces. In accordance with one aspect of the invention, multiple such PLCs can be integrated in a single custom IC.
According to an aspect of the invention, the PLC adapter provides both a built-in self-test controller for manufacturing test of the programmable logic array, as well as both initial and runtime verification of the configuration data stream to the programmable logic array. The configuration data stream can come from a configuration data source such as a serial PROM, or it can be a reconfiguration stream from an on-chip or off-chip processor. The PLC adapter further provides the ability to start, stop and single-step the system clock to the programmable logic array to allow for debugging, as well as to set breakpoints for issuing interrupts to a monitoring processor. According to a further aspect of the invention, the PLC adapter is designed separate from the programmable logic array, which array is designed according to the needs of the application.
According to another aspect of the invention, the ACI isolates the programmable logic from the rest of the custom IC circuitry for allowing diagnostics to be performed on each independently of the other. The ACI further provides support for a custom chip boundary scan chain for running Automatic Test Pattern Generated vectors on the application circuitry.


REFERENCES:
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patent: 6191603 (2001-02-01), Muradali et al.
patent: 6408412 (2002-06-01), Rajsuman
patent: 6492833 (2002-12-01), Asson et al.
patent: 6577158 (2003-06-01), Gupta

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