Programmable logic array having an on/off sense function

Details Programmable logic array having an on/off sense function Programmable logic array having an on/off sense function

1986-05-05

1989-03-21

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365196, 365233, 365185, 34082583, 34082587, G11C 700, G11C 1140

Patent

active

048150363

ABSTRACT:
A programmable logic array includes a plurality of semiconductor memory elements, such as FAMOSs, arranged in the form of an array and a sense circuit for receiving data out from the memory elements during read out mode. The present programmable logic array is so structured that the sense circuit is rendered operative for a predetermined time period every time when an input signal to the array changes its state thereby allowing to minimize the power consumption.

REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4313106 (1982-01-01), Hsu
patent: 4503520 (1985-03-01), Kyomasu et al.
patent: 4508977 (1985-04-01), Page et al.
patent: 4558435 (1985-12-01), Hsieh
patent: 4592028 (1986-05-01), Konishi
Konishi et al., "A 64 Kb CMOS RAM", IEEE Internat. Solid States Circuits Conf., Dig. of Tech. Papers, Feb. 12, 1982, pp. 258-259, 333.

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