Programmable interconnect structures

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C326S083000

Reexamination Certificate

active

07129744

ABSTRACT:
A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes.A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits.A method of forming a programmable interconnect structure for an integrated circuit comprises: fabricating one or more pass-gates on a substrate layer to electrically connect two points; and selectively fabricating either a memory circuit or a conductive pattern substantially above said pass-gates to control a portion of said pass-gates; and fabricating an interconnect and routing layer substantially above said memory circuits to connect said pass-gates and one of said memory circuits and conductive pattern.

REFERENCES:
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4706216 (1987-11-01), Carter
patent: 4761768 (1988-08-01), Turner et al.
patent: 4870302 (1989-09-01), Freeman
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 5861761 (1999-01-01), Kean
patent: 6134173 (2000-10-01), Cliff et al.
patent: 6239613 (2001-05-01), Reddy et al.
patent: 6262595 (2001-07-01), Huang et al.
patent: 6275065 (2001-08-01), Mendel
patent: 6448808 (2002-09-01), Young et al.
patent: 6515511 (2003-02-01), Sugibayashi et al.
patent: 6831481 (2004-12-01), Nguyen et al.
patent: 2004/0225980 (2004-11-01), Cappelli et al.
Seals & Whapshott, “Programmable Logic—PLDs and FPGAs”, 1997, pp. 102-117, McGraw-Hill, USA, no month.
Ashok K. Sharma, “Programmable Logic Handbook—PLDs, CPLDs, & FPGAs”, 1998, pp. 99-171, McGraw-Hill, USA, no month.
V. Betz, J. Rose, A. Marquardt, “Architecture and CAD for Deep-Submicron FPGAs”, Feb. 1999, Kluwer Academic Publishers, Boston.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable interconnect structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable interconnect structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable interconnect structures will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3653213

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.