Programmable formatter circuit for integrated circuit tester

Details Programmable formatter circuit for integrated circuit tester Programmable formatter circuit for integrated circuit tester

1997-08-29

1999-07-06

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

324765, G01R 3128

Patent

active

059192704

ABSTRACT:
A formatter circuit for channel of a multiple channel integrated circuit tester includes a drive control circuit, a compare circuit, and a random access memory (RAM). The RAM converts each value of input format selection data to corresponding format control data supplied to the drive control and compare circuits. The drive control circuit generates a set of drive control signals which determine the state of a test signal the tester channel supplies to a terminal of a device under test (DUT). The compare circuit determines whether a DUT output signal at the terminal is of an expected logic state. The drive and compare circuits employ multiplexers controlled by the format control data output of the RAM to select from among a variety of alternative data sources referencing desired states of the drive control signals or expected states of the DUT output signals. The formatter architecture permits flexible use of input reference data to provide a wide variety of selectable drive and compare formats.

REFERENCES:
patent: 5453995 (1995-09-01), Behrens
patent: 5479415 (1995-12-01), Staiger
patent: 5481549 (1996-01-01), Tokuyama
patent: 5579251 (1996-11-01), Sato
patent: 5590137 (1996-12-01), Yamashita
patent: 5659553 (1997-08-01), Suzuki
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patent: 5696772 (1997-12-01), Lesmeister
patent: 5717352 (1998-02-01), Ebiya
patent: 5732047 (1998-03-01), Niijima
patent: 5748642 (1998-05-01), Lesmeister
patent: 5789958 (1998-08-01), Chapman et al.

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