Programmable delay circuit having a fine delay element...

Details Programmable delay circuit having a fine delay element... Programmable delay circuit having a fine delay element...

1999-03-05

2002-07-16

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C327S276000

Reexamination Certificate

active

06421784

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to signal delay devices, and in particular to digital delay elements that are incrementally-adjustable for use with computer system components.
BACKGROUND INFORMATION
As the operation speed of computer systems continues to increase, the need exists to delay either clock or data signals to optimize the critical timing within the computer system due to the timing requirements of system components. Certainly, as the clock rate in the system increases, timing between the computer elements and within the computer chips becomes critical. One method to control the timing has been with a delay elements controllable through a digital Delay Locked Loop (“DLL”). These devices have been typically limited to coarse variable-delays where the incremental delay unit is one or two logic gates providing one or two block delay units, accordingly.
A design consideration for a delay element is its delay resolution and its insertion delay. The delay resolution is the unit of delay available through a delay element. Conventional delay circuits with block unit delays may be acceptable for low frequency operation, but high performance circuits require fractional increments of block delays. Insertion delay is the amount of delay generated by a delay element when at a zero delay state. The insertion delay is an important consideration particularly when deskewing data, since any added delay in a data path decreases overall performance.
In conventional delay circuitry, it is common-that the insertion delay is substantial and much larger than the minimum increment of increase in delay, as in the delay element illustrated in FIG.
5
. The insertion delay is large in this case due to the large number of inputs being multiplexed at the N:1 MUX. For example, the insertion delay may be 2 nanoseconds, while the increment of increase may be 0.2 nanoseconds. Alternatively, the insertion delay may be smaller, and the increment of increase may be of the same magnitude of the insertion delay, as in the delay element illustrated in FIG.
6
. However, it is generally the case, for this configuration, that the constituent 2:1 MUX delay elements must be matched in order to reduce signal distortion. Therefore, for the delay element in
FIG. 6
, if the insertion delay is small and largest selectable delay is to be substantial, a substantial number of delay elements must be included. For example, for the delay element in
FIG. 6
, if the insertion delay is to be 0.2 nanoseconds, then to achieve a maximum delay of 2.6 nanoseconds would require 13 MUX's.
Accordingly, a need exists for a programmable delay element for high performance computer systems that has greater delay resolution and negligible insertion delay. Also needed is a programmable delay element that does not distort signals passed through the circuit, either at large or small delay values, and is testable with relatively uncomplicated testing techniques.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing needs by providing circuitry for delaying a signal that includes a coarse delay element and a fine delay element. The coarse delay element is coupled to a delay element input node for receiving an input signal, and has an output node for outputting a coarse delay element output signal. The coarse delay element receives at least one control signal for selecting a delay time, the output signal being responsive to the input signal, and delayed with respect to the input signal according to the selected delay time. The fine delay element is coupled to the delay element input node for receiving the input signal, and is coupled to the coarse delay element output node for receiving the output signal from the coarse delay element. The fine delay element has an output node for outputting an output signal. The fine delay element receives at least one control signal for selecting the fine delay element delay time, and an operative input signal, from the delay element input signal and the coarse delay element output signal. The fine delay element output signal is responsive to the operative fine delay element input signal, and delayed with respect to the operative fine delay element input signal according to the selected fine delay element delay time.
A further aspect of the present invention is a method for delaying a signal. The method receives a delay element input signal by a coarse delay element, selects a coarse delay element delay time by at least one coarse delay element control signal, outputs a coarse element output signal by the coarse delay element responsive to the delay element input signal, and delayed with respect to the input signal according to the selected coarse delay element delay time. The method also receives the delay element input signal by a fine delay element, receives the coarse delay element output signal by the fine delay element, selects the delay element input signal or the coarse delay element output signal as an operative fine delay element input signal by at least one fine delay element control signal, selects a fine delay element delay time by at least one fine delay element control signal, and outputs a fine delay element output signal responsive to the operative fine delay element input signal, and delayed with respect to the operative fine delay element input signal according to the selected fine delay element delay time.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 4657406 (1987-04-01), Yaeda
patent: 5086500 (1992-02-01), Greub
patent: 5293626 (1994-03-01), Priest et al.
patent: 5463337 (1995-10-01), Leonowich
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5552726 (1996-09-01), Wichman et al.
patent: 5737767 (1998-04-01), Agrawal et al.
patent: 5777504 (1998-07-01), Chu et al.
patent: 6075415 (2000-06-01), Milton et al.
patent: 6166573 (2000-12-01), Moore et al.
patent: 6229367 (2001-05-01), Choudhury
patent: 3-035613 (1991-02-01), None
patent: 3-130678 (1991-06-01), None

Affiliated with

Also associated with

Rating

Programmable delay circuit having a fine delay element... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable delay circuit having a fine delay element..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable delay circuit having a fine delay element... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2839199